MOS Switch Bias Control for Low-Leakage Sample-and-Hold
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Solution Overview
Problem
Electronic switching devices in sample and hold applications experience instability due to leakage currents, which can discharge or charge capacitors to ground or power supply voltage, leading to voltage instability across capacitor terminals.
Innovation Solution
The method involves controlling a main MOS transistor to reduce leakage currents by applying specific bias voltages when in the on or off state, connecting the substrate and conducting electrode to the input terminal in the on state to lower the threshold voltage and resistance, and applying a second bias voltage to the substrate in the off state to minimize reverse junctions and leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the main transistor is kept in a standard configuration, then the device structure is simple, but leakage currents cause voltage instability during hold periods
Solution Approach 1:
The patent applies dynamics by making the transistor configuration adaptive rather than static. The main transistor dynamically switches between different operational modes (standard mode and leakage reduction mode) based on the control signal state. During hold periods, the transistor enters leakage reduction mode where the source is connected to the substrate and bias voltages are applied, automatically adapting to minimize leakage without requiring external intervention.
Solution Approach 2:
The patent changes physical parameters of the transistor operation by applying specific bias voltages to the source and substrate terminals. During hold periods, a first bias voltage is applied to the source and a second bias voltage to the substrate, changing the electrical parameters to reduce leakage currents. This parameter modification allows the same transistor to operate with different characteristics depending on the operational phase.
2Reliability
If bias voltages are applied to reduce leakage currents, then voltage stability improves, but additional control circuits and power consumption increase
Solution Approach 1:
The patent applies periodic action by implementing bias voltages only during hold periods when the transistor is off, rather than continuously. The control circuit switches between standard operation during sample periods and leakage reduction mode during hold periods. This periodic application of bias voltages reduces average power consumption while maintaining voltage stability when needed most.
Solution Approach 2:
The patent implements self-service through the main control signal that automatically controls both the main transistor gate and the bias voltage application. The same control signal that switches the main transistor on/off also triggers the bias voltage application, eliminating the need for separate control circuits. The system serves itself by using its primary control signal to manage leakage reduction, reducing overall control complexity and power consumption.
3Object-generated harmful factors
If the transistor width is reduced to minimize reverse junctions, then leakage currents decrease, but the on-state resistance increases and charging speed decreases
Solution Approach 1:
The patent applies dynamics by making the transistor width adaptive. During hold periods, the transistor width is reduced to minimize reverse junction leakage. During sample periods when charging is needed, the transistor width is increased to reduce on-state resistance and improve charging speed. This dynamic width adjustment allows the system to optimize for leakage reduction when the transistor is off and for fast charging when the transistor is on.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces leakage currents, allowing the capacitor to charge faster during sample periods and maintaining voltage stability during hold periods, particularly beneficial for low-power microcontrollers requiring stable voltage references.
Implementation Method 1
a main MOS transistor, for example an NMOS transistor or a PMOS transistor, having a gate, a source and a drain
Implementation Method 2
connecting the substrate and the source of the main transistor to the input terminal when the latter is in its on state makes it possible to reduce the threshold voltage of that transistor
Implementation Method 3
the reduction of the resistance of the main transistor in its on state makes it possible to reduce the width of the MOS transistor and therefore the size of the reverse junctions connected to the output terminal and to the source of the leakage currents
Data Source
AI summary
A method is used to control an electronic device that includes a switching unit having a main MOS transistor having a substrate, a first conducting electrode and a second conducting electrode coupled to an output terminal. The method includes controlling the main transistor in such a way as to put it into an on state or an off state such that, when the main transistor is in the on state, the substrate and the first conducting electrode of the main transistor are connected to an input terminal and, when the main transistor is in the off state, the first conducting electrode of the main transistor is isolated from the input terminal and a first bias voltage is applied to the first conducting electrode and a second bias voltage is applied to the substrate of the main transistor.