Receiver Buffer Circuit With AC Grounding for Accurate Sampling

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Solution Overview

Problem

Existing sample and hold circuits suffer from distortion of sampled values due to parasitic capacitors, especially at high data processing speeds, affecting the accuracy of analog-to-digital conversion.

Innovation Solution

Incorporation of a receiver circuit with a first capacitor and a buffer circuit comprising a transistor, where a reset switch is AC grounded to mitigate the influence of parasitic capacitors, ensuring accurate sampling and holding operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data processing speed increases, then productivity is improved, but the sampled value becomes distorted by parasitic capacitor

Engineering Contradiction:

Improvedata processing speedVSAvoidsampling accuracy

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The patent extracts and removes the parasitic capacitor's harmful influence by introducing a reset switch that discharges the parasitic capacitor during the sampling phase. This isolation technique separates the parasitic element from the signal path, allowing high-speed processing without distortion.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The reset switch performs a preliminary action by discharging the parasitic capacitor before the sampling operation begins. This preemptive measure prevents the parasitic capacitor from causing distortion during the actual sampling process, enabling accurate high-speed processing.

Inventive Principle:

Principle #9Preliminary anti-action

2Power

If buffer circuit is added to drive input capacity, then power is improved, but parasitic capacitor distortion occurs

Engineering Contradiction:

Improvedriving capabilityVSAvoidsampling accuracy

Core Design Contradiction:

PowerVSManufacturing precision

Solution Approach 1:

The patent converts the harmful parasitic capacitor into a beneficial element by using it in conjunction with the reset switch. The reset switch deliberately controls the parasitic capacitor's discharge, transforming what was previously a source of distortion into a manageable component that can be reset periodically, thus enabling both high power drive capability and accurate sampling.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

3Manufacturing precision

If reset switch is AC grounded, then parasitic capacitor influence is reduced, but circuit complexity increases

Engineering Contradiction:

Improvesampling accuracyVSAvoidcircuit structure

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies equipotentiality by AC grounding the reset switch during the sampling phase. This creates a virtual ground that equalizes the potential at the parasitic capacitor nodes, effectively nullifying its distorting influence. The AC ground provides a reference potential that stabilizes the circuit during critical operations.

Inventive Principle:

Principle #12Equipotentiality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed solution effectively minimizes distortion by maintaining a stable DC voltage, thereby enhancing the accuracy of the analog-to-digital conversion process.

Implementation Method 1

a first capacitor connected to a first node, the receiver circuit being configured to receive a first input voltage, and store a first charge corresponding to the first input voltage in the first capacitor during a first period

Methodology Applied

Scientific EffectCapacitance: Capacitance

Implementation Method 2

a buffer circuit comprising a first transistor including a gate terminal connected to the first node, a source terminal connected to a first output node which is configured to output a first output voltage corresponding to the first input voltage

Methodology Applied

Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 3

a drain terminal connected to a second node that is AC grounded during the first period

Methodology Applied

Scientific EffectParasitic capacitance: Parasitic Capacitance

Data Source

PatentUS20260074707A1Receiver circuit of interface circuit and operating method thereof

Publication Date: 2026.03.12 SAMSUNG ELECTRONICS CO LTD

AI summary

A receiver circuit includes: a first sampling circuit that includes a first capacitor connected to a first node, and is configured to receive a first input voltage, and store a charge corresponding to the first input voltage in the first capacitor during a first period; and a buffer circuit includes a first transistor including a gate terminal connected to the first node, a source terminal connected to a first output node which is configured to output a first output voltage corresponding to the first input voltage, and a drain terminal connected to a second node that is AC grounded during the first period.