Multi-Voltage ADC Data Path for PVT-Stable High Sampling Rates
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Solution Overview
Problem
As ADC sampling rates increase, time-interleaved ADCs become larger in implementation area, leading to increased loading of the analog front-end of receivers, and are sensitive to process, voltage, and temperature variations, which affect performance and power consumption.
Innovation Solution
A data path configuration using multiple voltage domains (VddH, VddM, VddL) for the AFE, THA, and TI-ADC, with PMOS and NMOS buffers to stabilize bandwidth, linearity, and speed under PVT variations, minimizing sampling switch variation and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If ADC sampling rate is increased, then data rate and signal-to-noise ratio are improved, but implementation area and loading on analog front-end increase
Solution Approach 1:
The ADC is divided into multiple parallel channels (e.g., four unit-ADCs) that operate at lower individual sampling rates. These channels are interleaved in time to achieve the overall high sampling rate, thereby distributing the implementation area across multiple smaller units rather than requiring one large high-speed ADC.
Solution Approach 2:
The patent transitions from a single-channel time-domain solution to a multi-channel time-interleaved architecture. By adding the channel dimension, the system achieves high effective sampling rates through temporal interleaving of multiple lower-rate channels, effectively trading spatial complexity for temporal multiplexing.
2Productivity
If ADC sampling rate is increased, then data rate is improved, but loading on analog front-end increases
Solution Approach 1:
The analog front-end loading is segmented across multiple parallel buffer circuits, each serving a specific ADC channel. This distribution reduces the burden on any single buffer and allows the analog front-end to drive multiple lower-rate channels rather than one high-rate channel, reducing overall loading stress.
3Productivity
If time-interleaved ADC structure is used, then sampling rate is improved, but sensitivity to process, voltage, and temperature variations increases
Solution Approach 1:
Each ADC channel is equipped with dedicated buffer circuits with optimized characteristics suited to that channel's specific requirements. The buffers can be independently designed and tuned to compensate for local PVT variations in each channel, ensuring consistent performance across all interleaved channels despite process, voltage, and temperature variations.
4Use of energy by moving object
If multiple voltage domains are used, then power consumption is optimized, but device complexity increases
Solution Approach 1:
Different voltage domains (VddH, VddM, VddL) are assigned to different circuits based on their specific performance requirements. The AFE uses VddH for high performance, the THA uses VddM for moderate performance with power optimization, and the ADCs use VddL for lower power consumption. This localized voltage assignment optimizes overall power consumption while managing complexity through systematic voltage domain separation.
Data Source
AI summary
An example data path to a receiver includes: an analog front-end circuit (AFE) configured to receive a first voltage supply; a first circuit coupled to an output of the AFE, the first circuit including: a first buffer having an input coupled to the output of the AFE; a second buffer; a first switch coupled between an output of the first buffer and an input of the second buffer; and a second switch coupled between an output of the second buffer and an input of an ADC of the receiver; wherein the first buffer is configured to receive the first voltage supply, the second buffer is configured to receive a second voltage supply, and the ADC is configured to receive a third voltage supply less than the first voltage supply.