Configurable Sample-and-Hold Circuit for LiDAR Frame Rate Tradeoffs
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Solution Overview
Problem
Existing LIDAR systems face challenges in achieving high sample rates without significantly reducing frame rates or increasing system complexity and cost, due to the need for interleaving low sample rate data or using high-speed ADCs, which limits their accuracy and efficiency in distance measurements.
Innovation Solution
A configurable sample-and-hold circuit that allows for adjustable time delays and sampling phases in each branch, enabling the collection of samples with different resolutions and optimizing the number of samples and averaging processes to improve resolution and frame rate, particularly by using a clock and timing circuit to set parameters for sampling instants and iterations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If interleaved low sample rate data is used to achieve high sample rate, then measurement precision is improved, but frame rate is reduced by a factor of N
Solution Approach 1:
The patent implements a configurable sample-and-hold array where the number of parallel channels N can be dynamically adjusted. By changing the value of N, the system can adapt between high-precision mode (larger N) and high-frame-rate mode (smaller N), allowing dynamic optimization based on application requirements rather than being fixed to a single operating mode
Solution Approach 2:
The system allows changing the sampling parameters including the number of parallel channels, sampling intervals, and time offsets as configurable parameters. This enables the effective sample rate and frame rate to be adjusted by modifying these parameters, resolving the contradiction by allowing both metrics to be optimized for different operational scenarios
2Measurement precision
If very high speed ADCs are used to achieve high sample rate, then measurement precision is improved, but device complexity and cost significantly increase
Solution Approach 1:
The patent divides the sampling task across N parallel sample-and-hold channels, each operating at a lower sample rate. This segmentation allows the use of simpler, lower-speed ADCs in each channel while achieving an effective high sample rate through the parallel architecture, thereby reducing the complexity and cost associated with using a single very high-speed ADC
Solution Approach 2:
The patent combines multiple low-speed sampling channels into a single high-effective-sample-rate data stream through interleaving. This merging approach achieves the functionality of a high-speed ADC system while using multiple lower-cost, lower-complexity components, thus reducing overall system complexity and cost
3Measurement precision
If more samples N are collected to increase effective sample rate, then measurement precision is improved, but frame rate is reduced by a factor of N
Solution Approach 1:
The patent makes the number of samples N a dynamic configurable parameter rather than a fixed value. Users can adjust N based on the specific measurement requirements and desired frame rate, allowing the system to adapt between collecting more samples for higher precision or fewer samples for higher frame rate, thus dynamically resolving the contradiction
Solution Approach 2:
The patent implements configurable time offsets between parallel channels, allowing partial overlapping of sample windows. This enables the system to collect slightly more or fewer samples than the minimum N required, providing flexibility to optimize the balance between measurement precision and frame rate based on specific application needs
Data Source
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AI summary
The present invention relates to a sample-and-hold circuit (100) comprising a plurality of sample-and-hold branches arranged in parallel and each comprising a buffer (107) and a sample-and-hold block (108) comprising one or more sample-and-hold cells (130). The sample-and-hold circuit is characterised in that the sample-and-hold circuit further comprises a clock and timing circuit (10) arranged for setting an adaptable time delay and phase for each sample-and-hold block.