Single-Stage High-Speed Sampling Circuit for Lower SERDES Delay
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Solution Overview
Problem
Existing high-speed serial receiving circuits face significant sampling delay due to two-stage sampling modules, which cannot meet the high-speed signal acquisition requirements of SERDES, DDR, and high-speed storage applications.
Innovation Solution
A high-speed sampling circuit is designed with a sampling module for amplifying differential input signals, a latch module for latching the output, and control modules for managing clock signals, utilizing NMOS and PMOS transistors to reduce transmission delay and improve signal sampling speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a two-stage sampling module is used, then the sampling circuit can function properly, but significant sampling delay occurs which cannot meet high-speed signal acquisition requirements
Solution Approach 1:
The patent extracts and removes one stage from the traditional two-stage sampling module, transforming it into a single-stage sampling circuit. This extraction eliminates the cumulative delay of multiple stages while maintaining the essential sampling function through direct coupling of the sampling switch to the latch module.
Solution Approach 2:
The patent merges the sampling and latching functions into a tightly integrated single-stage architecture. The sampling switch directly controls the latch without intermediate buffering stages, combining what were previously separate operational stages into a unified high-speed sampling unit that reduces overall delay.
2Productivity
If a two-stage sampling module is used, then the circuit provides sufficient signal processing, but the transmission delay increases reducing bandwidth performance
Solution Approach 1:
The patent extracts unnecessary intermediate processing stages from the traditional two-stage design, retaining only the essential sampling and latching functions. This extraction reduces transmission delay while preserving adequate signal processing capability for high-speed applications.
Solution Approach 2:
The patent changes the operational parameters of the sampling circuit by eliminating intermediate buffering stages and directly coupling the sampling switch to the latch module. This parameter change in the circuit architecture reduces transmission delay and improves bandwidth performance while maintaining signal processing adequacy.
Data Source
AI summary
A high-speed sampling circuit is disclosed which comprises a sampling module for amplifying a differential input signal; a latch module for latching the differential output signal of the sampling module; a first control module for controlling the sampling module under a first clock signal; a second control module for controlling the latch module under a second clock signal; a third control module for controlling control the output of the differential output signal under the second clock signal. The high-speed sampling circuit of the disclosure, after sampling the differential input signal, the sampling module outputs it to the latch module and controls the latch module to output the differential output signal, compared to the existing two-stage sampling module, it saves the transmission delay of the two-stage sampling module and can improve the performance of the high-speed sampling band of the signal.