Two-Stage Data Sampling Circuit With Integrated Decision Feedback Equalization
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Solution Overview
Problem
In low power double data rate (LPDDR) memories, the increasing signal transmission rate leads to channel loss, causing intersymbol interference, which existing equalizers fail to compensate for effectively without increasing power consumption.
Innovation Solution
A data sampling circuit incorporating a first and second sampling module, a latch module, and a decision feedback equalization module, along with an offset compensation module, to reduce intersymbol interference while minimizing power consumption by integrating decision feedback equalization in a parallel configuration with the second sampling module.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate equalizer is arranged at the receiver to compensate for channel loss, then intersymbol interference is reduced, but power consumption increases
Solution Approach 1:
The patent merges the equalizer function with the existing data sampling circuit by integrating a decision feedback equalization module that operates in parallel with the sampling modules. This combines multiple functions (sampling and equalization) into a single integrated circuit, avoiding the need for a separate equalizer and thus reducing power consumption while maintaining signal quality compensation
Solution Approach 2:
The data sampling circuit is designed to perform multiple functions: data sampling and decision feedback equalization. The circuit uses the same clock signals and node structures for both sampling operations and equalization computations, making the circuit universal and eliminating the need for dedicated separate equalizer hardware
2Productivity
If signal transmission rate is increased to improve data throughput, then productivity is improved, but channel loss increases causing more intersymbol interference
Solution Approach 1:
The patent implements a decision feedback equalization mechanism where the output of the latch module feeds back to the decision feedback equalization module. This feedback loop allows the circuit to compensate for intersymbol interference caused by high-speed transmission, enabling high data rates while maintaining signal quality through continuous correction of channel loss effects
Data Source
AI summary
Embodiments provide a data sampling circuit and a data sampling device. The sampling circuit includes: a first sampling module configured to respond to a signal from a data signal terminal and a signal from a reference signal terminal and to act on a first node and a second node; a second sampling module configured to respond to a signal from the first node and a signal from the second node and to act on a third node and a fourth node; a latch module configured to input a high level signal to a first output terminal and input a low level signal to a second output terminal or input the low level signal to the first output terminal and input the high level signal to the second output terminal according to a signal from the third node and a signal from the fourth node; and a decision feedback equalization module.