Differential Sample-and-Hold Circuit for Low-Noise ADC Sampling
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Solution Overview
Problem
Existing sample holding circuits are complex, occupy large space on circuit boards, and have a low signal-to-noise ratio during digital conversion of analog signals.
Innovation Solution
A simplified sample holding circuit design using two sampling units and a holding unit with equal capacitance values, where clock signals trigger switches to sample and hold voltages, effectively canceling noise interference and reducing circuit size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If existing sample holding circuit is used, then digital conversion function is achieved, but circuit structure becomes complicated and occupies large area
Solution Approach 1:
The circuit is divided into two independent sampling units (first sampling unit with first sampling capacitor, second sampling unit with second sampling capacitor) that operate in parallel. Each unit handles one polarity of the analog signal independently, simplifying the overall structure by eliminating the need for complex switching mechanisms and delay units required in traditional single-unit designs.
Solution Approach 2:
The two sampling units are merged with a common holding unit that simultaneously holds both the first sampling voltage and second sampling voltage. This integration reduces the total component count and circuit area compared to using separate holding circuits for each sampling unit, while maintaining the simplified parallel structure.
2Measurement precision
If existing sample holding circuit is used, then digital conversion function is achieved, but signal-to-noise ratio remains low
Solution Approach 1:
The circuit converts the potentially harmful effect of noise during sampling into a beneficial outcome by simultaneously sampling both polarities (positive and negative) of the analog signal. The differential processing of these two sampling voltages in the holding unit cancels out common-mode noise, improving the signal-to-noise ratio while maintaining a simple parallel circuit structure.
3Measurement precision
If conversion time is extended to ensure accuracy, then analog signal must remain unchanged, but circuit complexity increases
Solution Approach 1:
The circuit uses periodic clock signals to alternately trigger the first and second sampling units. This periodic sampling approach allows the analog signal to be captured at discrete intervals without requiring it to remain completely unchanged during the entire conversion process, reducing the need for complex signal stabilization mechanisms while maintaining conversion accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution simplifies the circuit structure, reduces noise interference, and improves the signal-to-noise ratio, enabling accurate digital conversion of analog signals without the need for additional delay or processing units.
Implementation Method 1
a first sampling capacitor CS1... a second sampling capacitor CS2... a first holding capacitor CF1... a second holding capacitor CF2
Data Source
AI summary
A sample holding circuit includes a signal input terminal, a first sampling unit, a second sampling unit, and a holding unit. The signal input terminal receives a first reference voltage or a second reference voltage, the first sampling unit samples the first reference voltage when a first clock signal is triggered to obtain a first sampling voltage, the second sampling unit samples the second reference voltage when a second clock signal is triggered to obtain a second sampling voltage. The holding unit receives the first sampling voltage and the second sampling voltage when a third clock signal is triggered. The sample holding circuit effectively simplifies circuit structure and reduces the use of amplifiers, also improving the signal to noise ratio.