Sample-and-Hold Circuit Topology for Reduced MOSFET Leakage
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Solution Overview
Problem
Sample-and-hold (S/H) circuits in modern ICs face limitations due to leakage currents, which reduce the hold time of sampled analog signals and increase power consumption, especially when switches implemented with MOSFETs experience sub-threshold, gate-induced leakage, body-drain, and diode leakage currents.
Innovation Solution
The implementation of a sample-and-hold circuit topology using multiple MOSFET switches and a native transistor to reduce leakage currents by controlling the voltage across switches, eliminating sub-threshold currents and limiting gate-induced and body-drain leakage, thereby extending hold time and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If MOSFET switches are used in S/H circuits, then the circuit can be integrated into modern ICs, but leakage currents increase and hold time decreases
Solution Approach 1:
The patent divides the single MOSFET switch into multiple segmented switches (first switch, second switch, third switch) with distinct functions. Each switch handles specific voltage ranges or leakage paths, allowing individual optimization of each segment to reduce overall leakage while maintaining integrability into ICs.
Solution Approach 2:
The patent introduces intermediate nodes and capacitors between the switches to mediate voltage transitions and isolate leakage paths. These intermediaries prevent direct leakage paths that would otherwise exist in a single-switch configuration, thereby extending hold time while preserving IC integrability.
2Ease of manufacture
If MOSFET switches are used in S/H circuits, then the circuit can be implemented with standard components, but sub-threshold and gate-induced leakage currents increase power consumption
Solution Approach 1:
The patent applies different quality characteristics to different parts of the circuit. The first switch operates in linear region with specific voltage characteristics, while the second and third switches operate in saturation region with different leakage profiles. This local optimization of each component's operating point minimizes overall power consumption while using standard MOSFET components.
Solution Approach 2:
The patent dynamically changes operating parameters (voltage levels, switch states) based on the sampling phase. During sample phase, switches are configured to minimize on-resistance; during hold phase, switches are reconfigured to minimize leakage currents. This parameter optimization reduces power consumption while maintaining ease of manufacture with standard components.
3Device complexity
If conventional S/H circuit topology is used, then the circuit structure is simple, but body-drain and diode leakage currents reduce hold time
Solution Approach 1:
The patent segments the conventional single-switch topology into multiple switches with dedicated leakage reduction functions. Each switch addresses specific leakage mechanisms (body-drain, diode, gate-induced), and the segmented structure maintains relatively simple overall circuit complexity while dramatically improving hold time.
Solution Approach 2:
The patent introduces asymmetric voltage control and switch configuration where each switch operates under different voltage conditions and control signals. This asymmetric design allows optimization of each switch's leakage characteristics, extending hold time without significantly increasing circuit complexity.
Data Source
AI summary
An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch coupled to provide an input signal to be sampled, and a second switch coupled to the first switch and to a first capacitor. The S/H circuit further includes a third switch coupled to the second switch and to a second capacitor, and a fourth switch to selectively couple to ground a node between the first and second switches.