In-Memory Compute Cell for Balanced Ternary Multiplication
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current in-memory computing devices for machine learning applications face challenges in scalability and energy efficiency due to limitations in storing and processing ternary weights, leading to suboptimal performance in digital accelerators for small end-user devices.
Innovation Solution
A compute cell design that stores ternary weights and uses a logic unit to selectively enable conductive paths for charging and discharging read bit lines based on the signs of the weights and input data, allowing for more dense storage and wider range of multiplication operations, enhancing energy efficiency and throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If standard 6T SRAM cells are used for in-memory computing with two-level quantization (+1/-1), then the device can be manufactured with existing technology, but the classification accuracy is limited and additional resources are needed to combine weak classifiers
Solution Approach 1:
The patent changes the quantization parameter from two-level (+1/-1) to three-level (0, +1, -1) weight representation. This allows stronger classifiers to be computed directly in the memory array without requiring combination of multiple weak classifiers, thereby improving classification accuracy while maintaining compatibility with standard SRAM cell manufacturing
Solution Approach 2:
The patent segments the weight representation into three distinct levels (0, +1, -1) rather than using only two levels. This segmentation enables more expressive weight values that can represent stronger classification boundaries, eliminating the need for additional classifier combination resources
2Productivity
If sub-threshold voltage operating condition is used to aggregate low bit cell currents, then a large number of memory cells can be read in parallel, but large variations in bit cell currents occur
Solution Approach 1:
The patent applies preliminary action by pre-charging the bit lines to a specific voltage level before reading the memory cells. This pre-charging compensates for the variations in bit cell currents that occur during sub-threshold operation, ensuring more reliable and consistent read outcomes across all memory cells in parallel
Solution Approach 2:
The patent implements beforehand cushioning by introducing pre-charging operations that cushion against the expected current variations. This pre-compensation mechanism ensures that even though individual cell currents vary, the aggregated result remains reliable and consistent
3Quantity of substance
If ternary weights are stored in compute cells with selective conductive paths, then storage density increases and wider range of multiplication operations are supported, but device complexity increases
Solution Approach 1:
The patent implements universality by designing a logic unit that handles multiple weight values (0, +1, -1) and multiple input scenarios through a unified structure. The same logic unit with selective conductive path enabling can represent different weight values and perform different multiplication operations, reducing the need for separate dedicated circuits for each weight value
Data Source
Figure 1~2
Figure 3~4
Figure 5~6
AI summary
A compute cell (10) for in-memory multiplication of a digital data input (X) and a balanced ternary weight (w) is disclosed and an in-memory computing device comprising an array thereof. The compute cell comprises a set of input connectors (11a, 11b) for receiving modulated input signals (A+, A-) representative of a sign and a magnitude of the digital data input, and a memory unit (12) configured for storing the balanced ternary weight. A logic unit (13) of the compute cell is connected to the set of input connector and the memory unit (12) to receive the data input and the balanced ternary weight, and is adapted to selectively enable one of a plurality of conductive paths for supplying a partial charge to a read bit line (S; S+, S-) during a compound duty cycle (T) of the set of input signals as a function of the respective signs of data input and ternary weight, and to disable each of the plurality of conductive paths if at least one of the balanced ternary weight and data input have zero magnitude. The compound duty cycle is indicative of the data input magnitude.