Cross-Coupled Sample-and-Hold Layout for Low Clock Feed-Through
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Solution Overview
Problem
Track and hold circuits in analog-to-digital converters face challenges with channel charge injection and channel conductance changes due to gate-to-source voltage and threshold voltage dependencies, limiting high-speed operation and introducing parasitic capacitance issues.
Innovation Solution
A sample and hold circuit design incorporating cross-coupled switches with dummy transistors not electrically connected to metal lines, minimizing parasitic capacitance and reducing feed-through effects, while maintaining high-frequency signal offset efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dummy transistors are electrically connected to metal lines to compensate for parasitic capacitance, then signal integrity is improved, but parasitic capacitance and clock feed-through increase
Solution Approach 1:
The patent creates dummy transistor regions that replicate the physical structure and parasitic characteristics of real transistor regions without establishing electrical connections. These dummy regions copy the capacitance profiles to adjacent metal lines, providing compensation for parasitic effects while avoiding the harmful feed-through that would result from actual transistor connections.
Solution Approach 2:
The dummy transistor regions act as intermediary structures between the functional transistors and the metal interconnect lines. They provide a passive capacitance interface that mediates the parasitic interaction, allowing the metal lines to be compensated for their parasitic effects without being directly connected to active switching elements that would introduce clock feed-through.
2Reliability
If dummy transistors are connected to metal lines, then parasitic capacitance compensation is achieved, but device complexity increases
Solution Approach 1:
Instead of creating complex connected dummy transistor circuits, the patent simply replicates the physical layout patterns of transistor regions without connections. This copying approach provides the necessary capacitance compensation while maintaining manufacturing simplicity and avoiding additional circuit complexity.
3Manufacturing precision
If standard transistor regions are used for dummy structures, then manufacturing consistency is improved, but unnecessary parasitic capacitance is introduced
Solution Approach 1:
The patent copies only the essential physical layout characteristics of transistor regions (such as active area geometry and positioning relative to metal lines) without including the full transistor structure. This selective copying maintains manufacturing consistency and layout regularity while avoiding the creation of actual parasitic capacitances that would arise from complete transistor structures.
Solution Approach 2:
The dummy regions are designed with locally optimized properties - they have the spatial distribution and geometric characteristics needed to provide capacitance compensation at specific locations adjacent to metal lines, but they deliberately lack the electrical connectivity and full structural features that would generate harmful parasitic effects.
Data Source
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AI summary
A sample and hold circuit may include: a first transistor connected between a first input terminal configured to receive a first input signal and a first output terminal configured to output a first sampled signal; a second transistor connected between a second input terminal configured to receive a second input signal and a second output terminal configured to output a second sampled signal; a first dummy transistor provided between the first input terminal and the second output terminal; and a second dummy transistor provided between the second input terminal and the first output terminal. A source region and a drain region of the first dummy transistor and a source region and a drain region of the second dummy transistor may not be electrically connected to a metal line connecting the first transistor with the second transistor.