Track-and-Hold Circuit With Clock-Feedthrough Cancellation
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Solution Overview
Problem
Existing track and hold systems in wireline SerDes applications face challenges in achieving high-speed, wideband performance with effective clock-feedthrough cancellation and signal equalization for high-speed serial data conversion.
Innovation Solution
A track and hold system utilizing a complementary source follower, built-in signal equalizer, clock generation with duty cycle control, and clock-feedthrough cancellation with amplitude control, employing non-overlapping switch clocks and amplitude-controlled clock signals to minimize distortion and enhance signal quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional track and hold system is used for high-speed serial data conversion, then the system can achieve basic tracking and holding functions, but it suffers from clock-feedthrough distortion and memory effects that degrade signal quality
Solution Approach 1:
The patent converts the harmful clock-feedthrough effect into a useful signal by capturing the clock feedthrough at the switch output and using it to generate a cancellation signal. This cancellation signal is then subtracted from the main signal path, effectively eliminating the distortion while maintaining high-speed operation capability
Solution Approach 2:
The patent applies preliminary anti-action by generating the clock-feedthrough cancellation signal in advance through a dedicated cancellation path that mirrors the main signal path. The cancellation signal is prepared and applied before the distorted signal affects the output, preventing the harmful effect from degrading signal quality
2Speed
If the switching speed is increased to achieve high-speed data conversion, then the tracking capability is improved, but nonlinear distortion and memory effects increase
Solution Approach 1:
The patent segments the signal path into multiple independent paths: a main signal path for high-speed tracking and a separate cancellation path for distortion removal. This segmentation allows each path to be optimized independently - the main path for speed and the cancellation path for precision, thereby resolving the contradiction between speed and signal accuracy
Solution Approach 2:
The patent introduces an intermediary cancellation signal that mediates between the high-speed switching action and the output signal. This intermediary signal carries the distortion information and enables its removal without affecting the main high-speed tracking function, thus maintaining both speed and accuracy
3Device complexity
If a simple track and hold circuit is used, then the device complexity is low, but it cannot provide effective clock-feedthrough cancellation and signal equalization
Solution Approach 1:
The patent merges the tracking function and clock-feedthrough cancellation function into a unified circuit architecture. The same switches and capacitors used for signal tracking also generate the clock-feedthrough signal, which is then fed into a cancellation path. This merging allows the system to achieve advanced distortion cancellation without proportionally increasing device complexity
Data Source
AI summary
A track and hold (TAH) system includes a complementary source follower circuit and a first TAH path. The complementary source follower circuit receives an input signal of the TAH system. The first TAH path includes a first TAH switch circuit, a first TAH output buffer circuit, and a first TAH clock-feedthrough cancellation circuit. The first TAH switch circuit is controlled by a first switch clock to sample a signal derived from an output signal of the complementary source follower circuit to obtain a first sampled signal. The first TAH output buffer circuit generates an output signal of the first TAH path according to the first sampled signal. The first TAH clock-feedthrough cancellation circuit applies clock-feedthrough cancellation to the first sampled signal according to the first switch clock.