Sample-and-Hold Circuit Topology for Low-Leakage Signal Retention

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Solution Overview

Problem

Sample-and-hold (S/H) circuits in modern ICs face limitations due to leakage currents, which reduce the hold time of sampled analog signals, leading to voltage decay and increased power consumption.

Innovation Solution

The implementation of a S/H circuit design using multiple MOSFET switches and a native transistor to minimize sub-threshold, gate-induced leakage, and body-drain currents by controlling switch states and voltages, thereby reducing leakage currents and extending hold time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Duration of action of stationary object

If a conventional S/H circuit is used, then the circuit can sample and hold analog signals, but leakage currents cause voltage decay and reduced hold time

Engineering Contradiction:

Improvehold timeVSAvoidleakage current

Core Design Contradiction:

Duration of action of stationary objectVSLoss of energy

Solution Approach 1:

The patent divides the single switching element into multiple MOSFET switches (first switch, second switch, third switch, fourth switch) arranged in a cascaded configuration. This segmentation allows each switch to be independently controlled and optimized to minimize different components of leakage current (sub-threshold, gate-induced, and body-drain currents), thereby extending the hold time of the sampled signal.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent changes the electrical parameters (voltages and switch states) of the MOSFETs dynamically between sample mode and hold mode. During hold mode, specific voltage levels are applied to the gates of the MOSFETs to minimize leakage currents. The native transistor adjusts its threshold voltage parameter to further reduce leakage, enabling extended hold time without significant voltage decay.

Inventive Principle:

Principle #35Parameter changes

2Duration of action of stationary object

If leakage currents are reduced by using multiple MOSFETs and native transistors, then hold time is extended, but device complexity increases

Engineering Contradiction:

Improvehold timeVSAvoidcircuit complexity

Core Design Contradiction:

Duration of action of stationary objectVSDevice complexity

Solution Approach 1:

The cascaded MOSFET structure serves multiple functions simultaneously: the first and second MOSFETs control the sampling and holding phases, the third and fourth MOSFETs manage the discharge and reset functions, and the native transistor provides threshold voltage adjustment. This multi-functionality reduces the need for additional separate circuit elements, thereby limiting the increase in overall device complexity while achieving extended hold time.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Measurement precision

If sampling is performed frequently to compensate for voltage decay, then signal accuracy is maintained, but power consumption increases

Engineering Contradiction:

Improvesignal accuracyVSAvoidpower consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The circuit performs preliminary action by establishing optimal voltage conditions and switch states before the hold period begins. The native transistor pre-adjusts its threshold voltage, and the MOSFETs are positioned in their optimal states during the sampling phase, so that during the extended hold period, minimal active control is needed. This preliminary configuration maintains signal accuracy throughout the extended hold time without requiring frequent re-sampling, thereby reducing power consumption.

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design enhances the hold time of sampled signals, reducing the need for frequent sampling and lowering power consumption during low-power modes by minimizing leakage currents, allowing for longer storage of output voltage.

Implementation Method 1

The S/H circuit includes a first metal oxide semiconductor field effect transistor (MOSFET) and a second MOSFET. The first and second MOSFETs are coupled in cascade to selectively provide power to a circuit.

Methodology Applied

Scientific EffectField effect transistor conduction: Conduction (electrical)

Implementation Method 2

The apparatus further includes a native transistor. The native transistor is coupled to provide a gate voltage of the second MOSFET.

Methodology Applied

Scientific EffectField effect transistor voltage control: Conduction (electrical)

Implementation Method 3

a fourth switch to selectively couple to ground a node between the first and second switches

Methodology Applied

Scientific EffectElectrical discharge to ground: Conduction (electrical)

Data Source

PatentUS11264111B2Reduced-leakage apparatus for sampling electrical signals and associated methods

Publication Date: 2022.03.01 SILICON LABORATORIES INC

AI summary

An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch coupled to provide an input signal to be sampled, and a second switch coupled to the first switch and to a first capacitor. The S/H circuit further includes a third switch coupled to the second switch and to a second capacitor, and a fourth switch to selectively couple to ground a node between the first and second switches.