Two-Stage Data Sampling Circuit With Parallel DFE and Offset Compensation
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Solution Overview
Problem
In low power double data rate (LPDDR) memories, increasing signal transmission rates lead to channel loss and intersymbol interference, which existing equalizers fail to address effectively due to increased power consumption.
Innovation Solution
A data sampling circuit integrating a decision feedback equalization module, with adjustable transistor parameters and a two-stage sampling structure, reduces intersymbol interference while minimizing power consumption by integrating the equalization module in parallel with the second sampling module and using offset compensation modules to reduce feedback noises.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate equalizer is arranged at the receiver to compensate for channel loss, then intersymbol interference is reduced, but power consumption increases
Solution Approach 1:
The equalization function is merged with the data sampling circuit by integrating the decision feedback equalization module with the sampling modules. The equalization is performed on the differential data signal during the sampling process itself, eliminating the need for a separate equalizer circuit. This combining approach achieves channel compensation while avoiding the additional power consumption of a standalone equalizer.
Solution Approach 2:
The data sampling circuit is designed to perform multiple functions: sampling the differential data signal and simultaneously performing decision feedback equalization. The circuit uses the sampled signals for both data recovery and equalization purposes, making the sampling circuit universal and eliminating the need for dedicated equalization hardware that would consume additional power.
2Reliability
If a decision feedback equalization module is integrated into the data sampling circuit, then intersymbol interference is reduced, but device complexity increases
Solution Approach 1:
The equalization process is segmented into discrete stages corresponding to the two sampling phases. The first sampling module processes one differential signal while the second sampling module processes the complementary signal, with each module having its own decision feedback equalization path. This segmentation allows the complex equalization function to be distributed across multiple simpler, parallel processing stages.
Solution Approach 2:
The decision feedback equalization is implemented using periodic sampling at two different phases. The circuit alternates between sampling the differential data signal and its complement in a periodic manner, with each phase contributing to the overall equalization. This periodic action transforms the continuous equalization problem into discrete, manageable sampling events that reduce circuit complexity.
Data Source
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AI summary
The present disclosure relates to a data sampling circuit and a data sampling device. The sampling circuit includes: a first sampling module configured to respond to a signal from a data signal terminal and a signal from a reference signal terminal and to act on a first node and a second node; a second sampling module configured to respond to a signal from the first node and a signal from the second node and to act on a third node and a fourth node; a latch module configured to, according to a signal from the third node and a signal from the fourth node, input a high level signal to a first output terminal and input a low level signal to a second output terminal, or input the low level signal to the first output terminal and input the high level signal to the second output terminal; and a decision feedback equalization module connected in parallel to the second sampling module and configured to reduce intersymbol interference. The data sampling circuit provided in the present disclosure can reduce intersymbol interference and have lower power consumption.