Distributed Current Reference Circuit for Cross-Point Memory Accuracy
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Solution Overview
Problem
Existing cross-point memory technologies face challenges in delivering accurate and low-power current references to highly distributed locations on a chip, which are prone to power and chip-area inefficiencies, and are sensitive to bias voltage noise, temperature variations, and supply voltage fluctuations.
Innovation Solution
A low-power, high-accuracy current reference system utilizing a source degeneration technique with active Metal-Oxide Semiconductor (MOS) devices and active biasing, which compensates for current, temperature, and supply variations, and maintains a sample-and-hold mode for long periods to reduce power consumption and area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a reference current is transferred from a central location to distributed current mirrors across the chip, then current reference accuracy can be maintained, but power consumption and chip area usage increase significantly
Solution Approach 1:
The patent divides the chip into multiple distributed tile current references instead of using a single central current reference. Each tile generates its own local current reference independently, eliminating the need for current transfer across the chip and reducing power consumption while maintaining accuracy at each location.
Solution Approach 2:
The patent extracts the current reference generation function from a centralized location and distributes it to multiple independent tile locations across the chip. Each tile contains its own current reference circuitry, removing the dependency on central current transfer and reducing overall power consumption.
2Area of stationary object
If bias voltage is remotely converted to reference current at multiple locations, then chip area usage is reduced, but the system becomes sensitive to bias voltage noise, temperature variations, and supply voltage fluctuations
Solution Approach 1:
The patent implements feedback mechanisms within each tile current reference circuit to compensate for variations. The feedback loops monitor and adjust for bias voltage noise, temperature variations, and supply voltage fluctuations, maintaining current reference stability despite environmental changes.
Solution Approach 2:
The patent uses parameter changes in the tile current reference circuits to compensate for environmental variations. By dynamically adjusting circuit parameters such as transistor gate voltages and current ratios, the system maintains accurate current references despite temperature and supply voltage changes.
3Measurement precision
If separate current reference sources are calibrated to remove mismatches, then current reference accuracy improves, but device complexity and calibration requirements increase
Solution Approach 1:
The patent designs all tile current references with identical circuit topologies and matching transistor pairs, ensuring homogeneous characteristics across the chip. This uniformity eliminates random device offsets and process variations, removing the need for complex calibration while maintaining high accuracy.
Solution Approach 2:
The patent uses current mirror circuits with matched transistors to create equipotential conditions across distributed tiles. By ensuring that corresponding nodes in different tiles are at the same potential, the system eliminates voltage mismatches and process variations without requiring calibration.
4Ease of operation
If distributed current references are implemented across the chip, then local current delivery is improved, but chip area usage increases
Solution Approach 1:
The patent designs the tile current reference circuit to perform multiple functions within a compact area: generating the local current reference, providing temperature compensation, and supplying bias voltages. This multi-functionality reduces the area required per tile while maintaining local current delivery capability.
Data Source
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AI summary
A highly distributed current reference for a solid-state memory comprises a centrally located current digital-to-analog converter (IDAC) and a plurality of remotely located tile current references. The IDAC comprises a first active device that generates a reference current, and a device that forms a first source degeneration resistance for the first active device. The IDAC outputs a voltage signal that represents a magnitude of the reference current. A remotely located tile current reference comprises a second active device and a device that forms a second source degeneration resistance for the second active device. The source degeneration resistances and capacitance coupled to the voltage signal output from the IDAC compensate for current, temperature, supply and process variations.