Current Mirror Biasing With Sample-and-Hold Noise Attenuation

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Solution Overview

Problem

Current mirror circuits in electronic circuits suffer from noise issues, particularly in narrow frequency bands, where traditional noise reduction methods either increase power consumption or require large capacitors that are impractical for incorporation.

Innovation Solution

A current mirror circuit design that incorporates a sample and hold circuit with a controller operating at a predetermined sampling frequency to attenuate bias noise, utilizing a small sample capacitor that quickly charges and retains voltage levels, effectively redistributing noise away from the frequency band of interest.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If a capacitor is added between the biasing transistor and the mirrored transistors to filter noise, then noise attenuation is improved, but the capacitor size becomes too large to be incorporated in a practical manner

Engineering Contradiction:
Improvebias noiseVSAvoidcapacitor size
Core Design Contradiction:
Object-affected harmful factorsVSVolume of stationary object

Solution Approach 1:

The patent applies periodic action by using a modulator to periodically modulate the bias noise signal at a high frequency, and then using a demodulator to demodulate the signal after filtering. This periodic modulation allows the use of a small capacitor to filter the modulated noise while maintaining effective noise attenuation in the baseband frequency range, resolving the contradiction between noise filtering effectiveness and capacitor size.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent changes the frequency parameter of the bias noise signal through modulation. By modulating the noise signal to a higher frequency, the filtering characteristics change, allowing a smaller capacitor to achieve the same effective noise attenuation. This parameter transformation resolves the contradiction between effective noise filtering and practical capacitor size constraints.

Inventive Principle:
Principle #35Parameter changes

2Object-affected harmful factors

If the magnitude of the reference current through the bias transistor is increased to reduce relative bias noise, then noise attenuation is improved, but power consumption increases

Engineering Contradiction:
Improvebias noiseVSAvoidpower consumption
Core Design Contradiction:
Object-affected harmful factorsVSUse of energy by stationary object

Solution Approach 1:

The patent changes the frequency parameter of the bias noise signal through modulation to a higher frequency. This allows the use of a small capacitor for filtering without requiring increased current magnitude. The modulation approach enables effective noise attenuation while maintaining the original low current levels, thus resolving the contradiction between noise reduction and power consumption.

Inventive Principle:
Principle #35Parameter changes

3Object-affected harmful factors

If a large capacitor is used to filter noise effectively, then noise attenuation is improved, but the circuit complexity and impracticality increase

Engineering Contradiction:
Improvebias noiseVSAvoidcircuit complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent introduces periodic modulation and demodulation stages that, while adding circuit elements, replace the need for a large capacitor. The modulator-demodulator pair with a small capacitor creates a practical filter solution that is less complex than implementing a large-capacitor filter, especially in integrated circuit contexts where large capacitors are difficult to implement.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentEP3152635B1Current mirror circuits with narrow bandwidth bias noise reduction
Publication Date: 2024.03.20 ROBERT BOSCH GMBH
  • EP3152635B1 patent drawingFigure 1
  • EP3152635B1 patent drawingFigure 2
  • EP3152635B1 patent drawingFigure 3

AI summary

A current mirror circuit includes a first transistor connected to a voltage source, a gate of the first transistor being connected to a drain of the first transistor, a current source connected to the drain and the gate of the first transistor, the current source being configured to generate a predetermined first output current, a sample and hold circuit having an input connected to the gate of the first transistor, a second transistor connected to the voltage source, a gate of the second transistor being connected to an output of the sample and hold circuit, and a controller operatively connected to the sample and hold circuit, the controller being configured to operate the sample and hold circuit at a predetermined sampling frequency to attenuate bias noise from the first transistor in a second output current from the second transistor.