Shared Sampling Circuit in TI-ADCs for Mismatch Calibration
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Solution Overview
Problem
Time-interleaved analog-to-digital converters (TI-ADCs) face distortion due to mismatches between sub-ADCs, leading to unwanted output distortion, which existing calibration methods struggle to fully address without requiring additional hardware or complex procedures.
Innovation Solution
A sampling circuit within the TI-ADC that combines an analog input signal with a test signal, using capacitors and switches to sample and process both signals during specific clock phases, allowing for calibration by generating a test signal, such as a pseudo-random binary sequence, to correct for gain and offset mismatches between sub-ADCs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a time-interleaved ADC structure is used to achieve high sampling rates, then the sampling rate is improved, but distortion due to sub-ADC mismatches increases
Solution Approach 1:
The patent implements background calibration that operates continuously during normal ADC operation, using feedback mechanisms to measure and correct sub-ADC mismatches in real-time without disrupting the high sampling rate operation
Solution Approach 2:
The calibration signal is pre-added to the ADC input along with the normal input signal, allowing mismatch correction to be performed in advance and continuously without requiring separate calibration operations that would interrupt normal operation
2Measurement precision
If background calibration is implemented by adding a calibration signal to the ADC input, then calibration capability is improved, but the need for additional parallel sub ADC hardware is eliminated
Solution Approach 1:
The patent merges the calibration function with the normal ADC operation by adding the calibration signal to the same input channel, allowing both calibration and signal processing to share the existing sub-ADC hardware without requiring additional parallel ADC channels
Solution Approach 2:
The existing ADC hardware is made multi-functional by enabling it to process both the normal input signal and the calibration signal simultaneously through the same sampling and conversion paths, eliminating the need for dedicated calibration hardware
3Measurement precision
If multiple sampling circuits are used for each sub ADC to improve calibration accuracy, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple sampling functions into a single shared sampling circuit that processes both the calibration signal and the normal input signal sequentially during different time periods, eliminating the need for separate sampling circuits for each function
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces distortion by enabling efficient calibration of sub-ADCs, eliminating the need for extra hardware and simplifying the calibration process, thereby improving the accuracy of the TI-ADC output.
Implementation Method 1
The sampling circuit comprises an input circuit comprising one or more capacitors, each having a first node and a second node. The sampling circuit comprises sampling switches connecting the first and second inputs with nodes of capacitors in the input circuit to sample the analog input signal and the test signal represented as electrical charges on capacitors in the input circuit
Implementation Method 2
The sampling circuit comprises an amplifier circuit and a first feedback switch connected between an output of the amplifier circuit and an input of the amplifier circuit. The first feedback switch is configured to be closed during a first clock phase and open during a second clock phase
Data Source
AI summary
An ADC includes a plurality of sub ADCs configured to operate in a time-interleaved manner and a sampling circuit configured to receive an analog input signal of the ADC, wherein the sampling circuit is common to all sub ADCs. The ADC includes a test signal generation circuit configured to generate a test signal for calibration of the ADC. The sampling circuit has a first input configured to receive the analog input signal and a second input configured to receive the test signal. The sampling circuit includes an amplifier circuit and a first feedback switch connected between an output of the amplifier circuit and an input of the amplifier circuit. The first feedback switch is configured to be closed during a first clock phase and open during a second clock phase, which is non-overlapping with the first clock phase.