Analog Neural Memory Input Circuitry for Tunable Synaptic Weights
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Solution Overview
Problem
Current hardware technologies for artificial neural networks lack adequate efficiency in terms of energy consumption and computational complexity, particularly due to the high cost and mediocre energy efficiency of digital supercomputers and graphics processing units compared to biological networks.
Innovation Solution
The development of input circuitry for an analog neural memory in a deep learning artificial neural network, utilizing non-volatile memory arrays as synapses, which allows for continuous analog programming and individual tuning of weight values, thereby mimicking biological neural networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If digital supercomputers or graphics processing units are used to achieve high computational parallelism, then the number of synapses and connectivity between neurons can be increased, but energy efficiency deteriorates and cost increases
Solution Approach 1:
The patent replaces digital computational systems (supercomputers, GPUs) with an analog neural network system implemented in CMOS technology. This substitution enables continuous analog programming of synapse weights and achieves high computational parallelism through analog circuit operations, fundamentally resolving the energy efficiency problem while maintaining high productivity
Solution Approach 2:
The patent changes the operational parameters from digital discrete values to continuous analog values for synapse weights. This allows for precise tuning of weight values and enables the system to achieve high computational parallelism with improved energy efficiency by operating in the analog domain rather than digital
2Use of energy by moving object
If CMOS analog circuits are used to implement synapses, then energy efficiency improves, but device area increases due to bulky circuit implementation
Solution Approach 1:
The patent segments the synapse implementation into distinct functional blocks including input circuitry, weight storage elements, and computation units. This segmentation allows for optimized area utilization while maintaining the energy-efficient analog operation, enabling compact implementation of neural network synapses
Solution Approach 2:
The patent transitions from two-dimensional planar circuit layouts to three-dimensional stacked architectures for the analog neural network. This dimensional change increases integration density and reduces the device area required while preserving the energy-efficient analog computation capabilities
3Adaptability or versatility
If non-volatile memory arrays are used as synapses, then continuous analog programming and individual tuning of weight values is enabled, but input circuitry complexity increases
Solution Approach 1:
The patent designs universal input circuitry that can interface with multiple types of non-volatile memory arrays while providing continuous analog programming capabilities. This multi-functional design reduces the overall complexity by using a standardized interface approach rather than custom circuitry for each memory type
Solution Approach 2:
The patent introduces intermediary circuit elements between the input signals and the non-volatile memory arrays that facilitate continuous analog programming. These intermediary components act as buffers and converters, managing the complexity of direct memory programming while enabling precise weight tuning
Data Source
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AI summary
Numerous embodiments of input circuitry for an analog neural memory in a deep learning artificial neural network are disclosed.