Analogue/Digital Conversion TRIZ Cases

Offset local-oscillator frequencies separate channel IF bands so multiple radar receive signals share one ADC, reducing chip area and sync issues.

Digital feedback reconstructs and subtracts receiver nonlinearities, improving high-frequency signal quality despite aging and temperature drift.

A shared sensing amplifier and switch matrix improve pixel switching-element sensing accuracy by avoiding capacitance mismatch and amplifier offset errors.

A tracking circuit samples, stores, and restores PLL tuning voltage to cut restart frequency error and speed locking after standby.

Window-sampling switches and closed-loop feedback create sampling-frequency notches, suppress aliasing, and preserve linearity and dynamic range.

Vertical bit transfer in column ADC circuits cuts horizontal line area while supporting faster CMOS image sensor frame rates and throughput.

Multiple sample-and-hold paths and ADCs raise sampling frequency, enabling more accurate and faster electronic pen position detection.

Continuous programming and readout let one memory array store neural weights in analog or digital form, improving precision and energy use.

Time-slot multiplexing across sensing circuits averages channel mismatch offsets and preserves accurate sensor readout under variable gain.

Bleed air pressure from the load compressor is used to diagnose APU power compressor health without extra sensors or confusion with turbine deterioration.

Internal voltage data comparison generates a flag for image sensor power anomalies, enabling timely alerts without complex external circuits.

Shared capacitors and conditional transmission-gate driving cut transistor count, area, and MAC errors in mixed-signal in-memory computing.

A charge-pump differential converter cuts PGA noise in silicon microphones, improving signal-to-noise ratio and power supply rejection.

On-chip bin power analysis enables phase-independent converter self-test without external equipment, cutting test cost while measuring SNR.

Weak reflected pulses trigger ADC dynamic range reduction, improving low-SNR LiDAR distance measurement for remote or low-reflectance objects.

Dual comparators with different reference slopes and gain selection cut ADC power and conversion time while protecting dark-region image quality.

A randomized DWA mismatch-shaping scheme cuts DAC spectral anomalies and distortion in digital microphone ADC assemblies.

A single switched auto-zero DAC calibrates multiple comparators, cutting chip area, power, dead time, and low-frequency noise.

Multi-tap ISI metering guides CTLE adaptation in SERDES receivers to speed convergence, resist drift, and reduce residual ISI.

Separate buffers isolate bootstrap-circuit currents from the signal path, reducing kickback while keeping switch on-resistance stable.

Phase-shifted ADC synchronization lets dual telescope receivers act as one larger sensor, extending range and improving distance accuracy.

Beat alignment uses cross-correlation to delay one audio stream before cross-fading, reducing audible discontinuities between sources.

Charge redistribution between switched capacitors creates a comparator threshold within the first bit time, cutting clock power and preamble delay.

Selectable resistor taps and bulk-controlled transistors improve low-power measurement of small sensor signals with lower noise and wider dynamic range.

Electrode-specific calibration and a master DAC improve implantable stimulator current accuracy and resolution across therapeutic ranges.

Real-time DAC clock modulation adds jitter and timing impairments to test waveforms, expanding baud-rate coverage for DUT stress testing.

A coarse-to-fine histogram narrows TDC depth analysis around the peak bin to improve resolution while reducing bin area and power.

A triple-path CDR uses fast and slow digital codes to track bandwidth across frequency corners while maintaining loop stability under jitter.

Continuous analog programming in non-volatile synapse arrays cuts neural hardware energy use while enabling precise weight tuning.

Capacitor-coupled weight storage reduces bit-line voltage variation, improving in-memory multiply accuracy and energy efficiency.

Alternating clock phases and gated dual-tail samplers cut PAM 4 kickback noise and power use while preserving sampling speed.

Digital logic and background calibration cancel DTC mismatch error in fractional-N PLLs, cutting jitter, spurs, and convergence time.

Sequential delay-stage triggering and event-counter binning average mismatch errors to improve time-of-flight distance accuracy.

Fly-back current is converted into a sigma-delta voltage signal to improve inductive sensing resolution without oscillator-frequency limits.

Without timer-based delay, this circuit filters rotary encoder bounce through edge detection and pulse reset for accurate decoding across varying speeds.

Direct feedback to the sampling circuit cuts DFE delay and expands pulse-width compensation to mitigate ISI and lower bit error rates.

A composite-signal reconstruction stage lets a wireless receiver decode high-code-rate inputs at a lower rate, cutting processing load and power.

Adaptive ADC thresholds and brief analog-domain timestamp storage help LIDAR detect near and far echoes with lower power and bandwidth.

Switching between standard and polyphase IIR filters cuts audible transients during mode changes while preserving digital microphone reconstruction quality.

A learned transmission-path model suppresses distortion and spectral leakage in delta-sigma modulation, improving RoF signal quality.

Threshold-based path selection lets segmented conditioning circuits handle wide input voltages with better sampling accuracy and lower circuit complexity.

A sliding rotary encoder on a helical cable enables direct, precise elevator position measurement without wire tensioning or complex sensors.

A switchable connection node changes impedance and voltage between amplifier stages to improve CDS noise reduction in photodetection circuits.

A demultiplexed PAM-2M decoder uses one extra-bit ADC for error detection and adaptive calibration to improve decoding while lowering power.

A shared interleaved CIC filter decimates multiple MEMS sensor signals with one processing path, cutting chip area and power use.

By using parasitic capacitance instead of a load resistor, this image sensor ramp circuit cuts latency, lowers power use, and improves ADC linearity.

Cascaded Mach-Zehnder modulators use optical nonlinearity to extend waveform bandwidth and temporal resolution while preserving SNR and dynamic range.

User-set filter data lets one sensor A/D circuit apply multiple digital filtering characteristics without adding fixed filter hardware.

A single dual-slope ramp generator supports HDR image sensing across analog gains while cutting circuit area and power.

Non-overlapping input and output phases let a time-delay VTVA improve linearity, speed, and PVT robustness in pipelined ADCs.