Column ADC Bit Transfer Layout for High-Frame-Rate Image Sensors
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Solution Overview
Problem
CMOS image sensors face challenges in achieving high-speed operation and reducing the area occupied by horizontal signal lines, which are necessary for increasing frame rate and throughput.
Innovation Solution
The design incorporates a CMOS image sensor circuit with column analog/digital conversion circuits that utilize storage elements and transfer paths to serially and vertically transfer bit data, allowing for parallel output of A/D-converted data to a post-stage logic circuit, reducing the need for dense horizontal signal lines and minimizing area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If n horizontal signal lines are used to transfer n-bit pixel data in parallel, then the frame rate and throughput are increased, but the area occupied by signal lines becomes large
Solution Approach 1:
The patent changes the data transfer direction from horizontal to vertical. Instead of using n horizontal signal lines to transfer n-bit pixel data in parallel, the invention uses vertical transfer paths within column ADC circuits to transfer data sequentially from storage elements to output, thereby reducing the area occupied by horizontal signal lines while maintaining high frame rate capability
Solution Approach 2:
The patent divides the n-bit pixel data into n separate bit data pieces, each stored in a dedicated storage element (first to n-th storage elements). Each storage element and its associated transfer path operate independently, allowing sequential transfer of individual bits through vertical paths rather than requiring parallel horizontal signal lines for all bits simultaneously
2Productivity
If n horizontal signal lines are used to transfer n-bit pixel data in parallel, then the throughput is increased, but the area occupied by signal lines becomes large
Solution Approach 1:
The patent changes the data transfer direction from horizontal to vertical. Instead of using n horizontal signal lines to transfer n-bit pixel data in parallel, the invention uses vertical transfer paths within column ADC circuits to transfer data sequentially from storage elements to output, thereby reducing the area occupied by horizontal signal lines while maintaining high throughput capability
Solution Approach 2:
The patent divides the n-bit pixel data into n separate bit data pieces, each stored in a dedicated storage element (first to n-th storage elements). Each storage element and its associated transfer path operate independently, allowing sequential transfer of individual bits through vertical paths rather than requiring parallel horizontal signal lines for all bits simultaneously
Data Source
AI summary
An image sensor circuit includes a plurality of column analog/digital conversion circuits each including: first to n-th storage elements configured to respectively store first to n-th pieces of bit data that constitute analog/digital-converted data obtained by analog/digital-converting analog signals outputted by pixels, where n is an integer greater than or equal to 2; first to (n−1)-th transfer paths configured to respectively transfer the bit data stored in the first to (n−1)-th storage elements from the first to (n−1)-th storage elements to the second to n-th storage elements; and an n-th transfer path configured to transfer the bit data stored in the n-th storage element from the n-th storage element to outside the plurality of column analog/digital conversion circuits.