CTLE Adaptation Using Multi-Tap ISI Metering in SERDES Receivers

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Solution Overview

Problem

Existing SERDES circuits face issues with convergence time, monotonicity, divergence, sensitivity to voltage and temperature drifts, and require inefficient tuning methods for channel equalization.

Innovation Solution

A SERDES circuit with a continuous-time linear equalizer (CTLE) using multi-tap ISI metering for robust and efficient tuning, incorporating ISI component weights to shape pulse response and reduce residual ISI through adaptive equalization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional equalizers are used for channel equalization, then equalization function is provided, but convergence time is considerable and convergence monotonicity and divergence issues occur

Engineering Contradiction:
Improveconvergence stabilityVSAvoidconvergence time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent changes the operating parameters of the CTLE by dynamically adjusting its tap weights based on measured ISI components. This allows the equalizer to adapt to different channel conditions and converge faster without monotonicity or divergence issues, directly resolving the contradiction between convergence stability and convergence time.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent implements a feedback mechanism where the measured ISI components are used to adjust the CTLE tap weights. This closed-loop control ensures stable convergence by continuously monitoring and correcting the equalization process, eliminating divergence issues while maintaining fast convergence.

Inventive Principle:
Principle #23Feedback

2Reliability

If conventional equalizers are used for channel equalization, then equalization function is provided, but sensitivity to voltage drifts and temperature drifts occurs

Engineering Contradiction:
Improveequalization performanceVSAvoidsensitivity to drifts
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The patent enables the equalizer to self-adjust by measuring ISI components and automatically modifying CTLE tap weights. This self-service capability allows the system to compensate for voltage and temperature drifts without external intervention, maintaining equalization performance while reducing sensitivity to environmental variations.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent transforms the static CTLE configuration into a dynamic system that continuously adapts its tap weights based on real-time ISI measurements. This dynamic adjustment capability allows the equalizer to track and compensate for drifts in voltage and temperature, improving reliability while reducing sensitivity to environmental changes.

Inventive Principle:
Principle #15Dynamics

3Measurement precision

If multi-tap ISI metering with weighted sum is used, then robust and efficient tuning is achieved, but device complexity increases

Engineering Contradiction:
Improvetuning accuracyVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the ISI measurement into multiple taps, each measuring a specific ISI component. This segmentation allows precise measurement of different interference components while organizing the complexity into manageable, modular units that can be processed systematically.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent creates a universal tuning mechanism where the multi-tap ISI meter and weighted sum calculation can be applied to various CTLE configurations and channel conditions. This multi-functional approach achieves robust and efficient tuning across different scenarios without proportionally increasing device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12388684B2Serdes circuit CTLE adaptation using ISI metering
Publication Date: 2025.08.12 ALTERA CORP
  • US12388684B2 patent drawing
  • US12388684B2 patent drawing
  • US12388684B2 patent drawing

AI summary

A CTLE-based SERDES receiver circuit using ISI metering provides an improved SERDES I/O performance. The CTLE SERDES receiver circuit may include an analog receiver frontend to generate an analog-to-digital converter (ADC) digital signal and a reduced ISI signal, a data path circuit to generate a sliced data stream and sliced cursor error stream, a digital signal processing (DSP) circuit to generate a converged data stream, a multi-tap intersymbol interference (ISI) assessment circuit to generate a weighted ISI sum, and an ISI minimization circuit to generate a continuous time linear equalizer (CTLE) adaptation control signal based on the weighted ISI sum.