PAM-2M Decoder Architecture With Mixed-Resolution ADCs
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Solution Overview
Problem
Existing receivers for converting serial input data into parallel output data in PAM-2M format face challenges in achieving enhanced performance and reduced power consumption simultaneously.
Innovation Solution
A decoder system comprising a demultiplexer and multiple analog-to-digital converters (ADCs) is introduced, where one ADC is an (M+1)-bit ADC for error detection and the others are M-bit ADCs for data conversion, along with a decoder device and a receiver that includes channel compensation, voltage regulation, phase interpolation, and adaptive control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ADC-based receivers are used for PAM-2M decoding, then performance can be maintained, but power consumption increases
Solution Approach 1:
The receiver is divided into multiple functional modules: channel compensator, voltage regulator, phase interpolator, decoder device, and adaptive controller. Each module performs a specific function, allowing for optimized power management while maintaining overall performance. The segmentation enables selective activation of components based on operating conditions.
Solution Approach 2:
The system dynamically adjusts multiple parameters including gain of the channel compensator, magnitude of reference voltage from the voltage regulator, phase shift of interpolated clock signals, and delay of deskewed clock signals. These parameter changes enable adaptive optimization of performance while minimizing power consumption under different channel conditions.
2Measurement precision
If high-precision ADCs are used for accurate data conversion, then decoding accuracy improves, but device complexity and power consumption increase
Solution Approach 1:
The voltage regulator acts as an intermediary between the power supply and ADCs, providing a precisely controlled reference voltage that enhances ADC accuracy without requiring higher-resolution converters. The channel compensator serves as another intermediary that pre-processes signals to reduce the burden on ADC precision requirements.
Solution Approach 2:
The adaptive controller implements feedback mechanisms by monitoring decoded output and error portions, then adjusting the gain of channel compensator, magnitude of reference voltage, phase shift, and delay parameters. This closed-loop feedback system maintains high decoding accuracy while avoiding the need for overly complex high-precision ADC hardware.
3Productivity
If multiple full-resolution ADCs are used for parallel data processing, then productivity increases, but power consumption and device complexity increase
Solution Approach 1:
Multiple N-bit first demultiplexed data signals are merged and buffered to form a single to-be-decoded data signal, which is then processed by shared channel compensation and voltage regulation circuits. This merging approach maintains high data throughput while reducing redundant power consumption in support circuits.
Solution Approach 2:
The system dynamically configures the operation of ADCs and demultiplexers based on input data conditions and channel characteristics. The adaptive controller adjusts operational parameters in real-time, allowing the system to maintain high productivity when needed while reducing power consumption during less demanding operating conditions.
Data Source
AI summary
A decoder includes a demultiplexer and a number (P) of ADCs, where P≥2. The demultiplexer receives a to-be-decoded data signal that is in a PAM-2M format, and demultiplexes the to-be decoded data signal into a number (P) of demultiplexed data signals, where M≥2. The ADCs respectively receive the demultiplexed data signals. One of the ADCs is an (M+1)-bit ADC, and converts the corresponding demultiplexed data signal into a digital first decoded signal that contains an M-bits wide data portion and a one-bit wide error portion. Each of the other one(s) of the ADCs is an M-bit ADC, and converts the corresponding demultiplexed data signal into a digital second decoded signal that contains an M-bits wide data portion.