PLL Tuning Voltage Tracking for Fast Mission-Standby Switching
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Solution Overview
Problem
Phase-locked loops (PLLs) in wireless communication devices experience significant initial frequency errors and slower locking times when switching between mission and standby modes, particularly due to temperature drift and loss of tuning voltage during standby periods.
Innovation Solution
Incorporating a tracking circuit that samples and saves the control voltage of the PLL during mission mode and restores it when reentering mission mode, reducing initial frequency errors and improving locking speed by maintaining a stable tuning voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the PLL is stopped during standby mode to save power, then energy consumption is reduced, but initial frequency error increases and locking time increases when restarting
Solution Approach 1:
The patent applies preliminary action by sampling and storing the tuning voltage value before the PLL enters standby mode. When the PLL restarts, this pre-stored voltage value is restored, allowing the PLL to resume operation with minimal frequency error and reduced locking time. This resolves the contradiction by preparing the system in advance rather than dealing with frequency drift after standby.
Solution Approach 2:
The patent uses copying by creating a digital representation (copy) of the analog tuning voltage value. The sample-and-hold circuit captures the voltage, and an ADC converts it to a digital value that can be stored in memory. When restarting, this digital copy is converted back to analog form to restore the original voltage, avoiding the need to physically maintain the voltage during standby while enabling fast restart.
2Measurement precision
If the PLL operates continuously in mission mode to maintain frequency accuracy, then initial frequency error is reduced, but energy consumption increases
Solution Approach 1:
The system performs preliminary sampling of the tuning voltage before entering standby mode, capturing the frequency state information. This allows the PLL to maintain frequency accuracy knowledge without continuous operation, reducing power consumption while preserving the ability to quickly restore accurate frequency when resuming mission mode.
Solution Approach 2:
The tracking circuit automatically samples, stores, and restores the tuning voltage without external intervention. The system serves itself by maintaining its own frequency state information through the sample-and-hold circuit and memory, eliminating the need for continuous high-power operation while preserving frequency accuracy.
3Device complexity
If temperature drift is allowed during standby mode, then device complexity is reduced, but frequency stability deteriorates when reentering mission mode
Solution Approach 1:
The patent applies preliminary action by capturing the tuning voltage value before temperature drift occurs during standby. The sample-and-hold circuit stores this voltage reference, and upon returning to mission mode, the system restores this pre-captured value to compensate for any temperature-induced frequency drift, maintaining stability without complex temperature compensation circuits.
Data Source
AI summary
Methods and apparatus for storing a control voltage of a phased-locked loop (PLL) when switching from mission mode to standby mode for the PLL, and for restoring the control voltage of the PLL when switching back to mission mode. An example PLL circuit includes a charge pump, a voltage-controlled oscillator (VCO) having a control input coupled to an output of the charge pump via a node, and a tracking circuit coupled to the node. The tracking circuit is generally configured to sample a voltage of the node during a mission mode, save a representation of the sampled voltage before entering a standby mode, and restore the sampled voltage to the node for reentering the mission mode using the saved representation of the sampled voltage.