Waveform Sensor Sampling Circuit for Higher-Frequency Pen Detection
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Solution Overview
Problem
Existing waveform sensors face challenges in improving the frequency of sampling, which affects the accuracy and efficiency of detecting the position of electronic pens or similar devices using sinusoidal signals.
Innovation Solution
The proposed solution involves a circuit configuration with multiple sample-and-hold circuits and analog-to-digital converters, controlled by a controller to optimize sampling timing and frequency, allowing for higher sampling rates, such as up to 8 MHz in one column, and further enhanced by dynamic range adjustments in the RAMP signal to improve sampling frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single sample-and-hold circuit and ADC are used, then the device complexity is low, but the sampling frequency is limited and cannot be improved
Solution Approach 1:
The patent divides the sampling system into multiple independent sample-and-hold circuits (first, second, third, fourth) and multiple ADC circuits, each handling different timing intervals. This segmentation allows parallel sampling operations that achieve higher effective sampling frequency (up to 8 MHz) without requiring a single complex high-speed converter, thus resolving the contradiction between sampling frequency and device complexity.
Solution Approach 2:
The patent introduces a time-multiplexed dimension by using multiple sample-and-hold circuits operating at different timing intervals (first timing, second timing, third timing, fourth timing). This temporal dimensionality allows the system to achieve high sampling rates by distributing samples across multiple circuits and time slots, effectively increasing productivity without proportionally increasing overall system complexity.
2Productivity
If multiple sample-and-hold circuits and ADC circuits are used to increase sampling frequency, then the sampling frequency is improved, but the device complexity increases
Solution Approach 1:
The patent merges multiple sample-and-hold circuits and ADC circuits into a unified controlled system where a single controller coordinates the operation of all circuits. This merging approach allows the system to achieve high sampling frequency through parallel processing while managing complexity through centralized control logic, rather than requiring independent complex systems for each sampling channel.
Solution Approach 2:
The controller serves multiple functions simultaneously: it controls the timing of multiple sample-and-hold circuits, coordinates the operation of multiple ADC circuits, and manages the overall sampling sequence. This multi-functionality reduces the need for separate control mechanisms for each circuit, thereby improving sampling frequency capability while limiting the increase in overall device complexity.
Data Source
AI summary
A circuit including a first circuit, a second circuit and a controller is provided, the first circuit and the second circuit each including a sample-and-hold circuit configured to hold a level of an input signal of a specific timing and an analog-to-digital converter circuit configured to convert the level of the input signal held in the sample-and-hold circuit into digital data and to output the digital data, the controller being configured to cause the first circuit to output the level of the input signal of a first timing and to cause the second circuit to output the level of the input signal of a second timing.