Decision Feedback Equalization With Direct Sampling Feedback
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Solution Overview
Problem
Existing DFE circuits in memory devices face challenges in achieving high-speed data transmission due to significant feedback delay and limited compensation space, which increases the bit error rate caused by inter-symbol interference (ISI).
Innovation Solution
The proposed solution involves a DFE architecture that reduces feedback delay by feeding back the output signal directly to the sampling circuit, without going through the CML circuit, and includes adjustable pulse width compensation space using equalizing circuits and capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the output signal is fed back through the CML circuit in existing DFE architectures, then the feedback path is complete, but the feedback delay increases significantly
Solution Approach 1:
The patent extracts the output signal feedback path from the CML circuit and feeds it directly to the sampling circuit, bypassing the CML circuit entirely. This extraction of the feedback path from the main signal processing chain eliminates the delay introduced by the CML circuit while maintaining the完整性 of the feedback loop.
Solution Approach 2:
The patent introduces a direct feedback path as an intermediary channel that carries the output signal directly from the output to the sampling circuit. This intermediary path avoids the congested CML circuit route and provides a low-delay feedback channel.
2Loss of time
If the feedback delay is reduced by bypassing the CML circuit, then the feedback path becomes shorter, but the compensation space for pulse width adjustment is limited
Solution Approach 1:
The patent introduces adjustable pulse width compensation circuits that can dynamically adjust the pulse width of the feedback signal. This dynamic adjustment capability allows the system to adapt to different channel conditions and interference levels, providing versatility despite the shortened feedback path.
Solution Approach 2:
The patent changes the pulse width parameter of the feedback signal through adjustable compensation circuits. By modifying this temporal parameter, the system can compensate for ISI effects and adapt to different transmission conditions, thereby increasing the compensation space.
3Device complexity
If existing DFE circuits use standard feedback paths, then the circuit structure is simple, but the bit error rate increases due to inter-symbol interference
Solution Approach 1:
The patent applies preliminary equalization by adjusting the pulse width of the feedback signal before it is combined with the input signal. This preliminary action compensates for anticipated ISI effects, reducing the bit error rate before the decision-making process occurs.
Solution Approach 2:
The patent implements a direct feedback mechanism where the output signal is fed back to the sampling circuit with adjustable pulse width compensation. This feedback loop continuously corrects for ISI effects, significantly reducing the bit error rate compared to systems without such feedback.
Data Source
AI summary
Electronic circuits, memory devices, and methods for compensating for data distortion from channel loss are provided. In one aspect, an electronic circuit includes a converter circuit configured to convert an input signal to a digital signal and a compensation circuit coupled to the converter circuit. The converter circuit includes a sampling circuit configured to receive the digital signal and generate an output signal. The output signal includes a stream of bits to be transmitted at a plurality of consecutive clock cycles. The converter circuit also includes one or more equalizing circuits coupled to the sampling circuit. Each equalizing circuit is configured to receive a bit of an output feedback signal at one of the consecutive clock cycles. The sampling circuit is configured to generate the output signal based on the digital signal and a sum of one or more equalization outputs of the one or more equalizing circuits.