Triple-Path CDR Oscillator for Jitter-Stable Bandwidth Tracking
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Solution Overview
Problem
Oscillator circuits in clock and data recovery (CDR) systems face challenges with large jitter due to process variations, temperature variations, and timing uncertainties in high-speed data transmission.
Innovation Solution
A clock and data recovery circuit with a triple-path structure for bandwidth tracking, which includes a sampling circuit, phase detector, processing circuits, and an oscillator circuit. The oscillator circuit generates an output clock based on detection results and digital codes from the processing circuits, allowing for phase and frequency adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the oscillator circuit operates at high speed for high-speed data transmission, then productivity is improved, but jitter increases due to process variations, temperature variations, and timing uncertainties
Solution Approach 1:
The patent implements a triple-path structure with dynamic path selection that adapts to different frequency corners. The system dynamically switches between paths based on operating conditions, allowing the oscillator to maintain high-speed operation while compensating for jitter through adaptive control mechanisms. This dynamic adaptation resolves the contradiction by enabling high productivity while maintaining reliability through real-time adjustments.
Solution Approach 2:
The patent changes operational parameters by implementing bandwidth tracking that adjusts loop bandwidth based on frequency corners. The system modifies control parameters dynamically to optimize performance at different operating points, allowing high-speed transmission while managing jitter through parameter optimization. This resolves the contradiction by adapting parameters to maintain both speed and stability.
2Adaptability or versatility
If the oscillator circuit uses a wide tuning range to accommodate temperature variations, then adaptability is improved, but manufacturing precision deteriorates due to increased complexity in maintaining accuracy across the range
Solution Approach 1:
The patent divides the frequency tuning range into multiple segments or frequency corners, each handled by specific paths in the triple-path structure. Rather than attempting to cover the entire range with a single optimized circuit, the system segments the operating range and uses different configurations for different segments. This segmentation allows wide adaptability while maintaining precision within each segment, resolving the contradiction between tuning range and manufacturing precision.
Solution Approach 2:
The system dynamically switches between different operational modes and paths based on the required frequency corner. This dynamic reconfiguration allows the oscillator to maintain high precision at any given frequency while providing wide overall tuning range. The adaptive switching mechanism resolves the contradiction by optimizing precision for the current operating point while maintaining capability across the full range.
3Device complexity
If the CDR circuit uses a single-path structure, then device complexity is reduced, but bandwidth tracking capability is insufficient to maintain loop stability at various frequency corners
Solution Approach 1:
The triple-path structure implements multi-functionality where each path is optimized for specific frequency corners or operating conditions. The system can universally handle various frequency ranges and stability requirements by selecting appropriate paths. This multi-functional design resolves the contradiction by providing comprehensive bandwidth tracking capability across all frequency corners while maintaining reasonable complexity through specialized optimization of each path.
Solution Approach 2:
The system dynamically selects and switches between different paths based on the operating frequency corner and stability requirements. This dynamic path selection allows the circuit to adapt its complexity to the specific operating conditions, using only the necessary paths for current requirements. This resolves the contradiction by maintaining loop stability through adaptive configuration while avoiding unnecessary complexity in any single operating mode.
Data Source
AI summary
A clock and data recovery circuit includes a sampling circuit, a phase detector, a first processing circuit, a second processing circuit and an oscillator circuit. The sampling circuit is configured to sample input data according to an output clock, and generate a sampling result. The phase detector is configured to generate a detection result according to the sampling result. The first processing circuit is configured to process the sampling result to generate a first digital code. The second processing circuit is configured to accumulate a portion of the first digital code to generate a second digital code. A rate of change of a code value of the second digital code is slower than a rate of change of a code value of the first digital code. The oscillator circuit is configured to generate the output clock according to the detection result, the first digital code and the second digital code.