Fractional-N PLL DTC Linearization via Mismatch-Noise Cancellation
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Solution Overview
Problem
Existing digital fractional-N phase-locked loops (PLLs) face challenges in achieving low jitter due to excessive error from component mismatches in digital-to-time converters (DTCs), which are necessary for quantization noise cancellation (QNC).
Innovation Solution
A digital-to-time converter mismatch-noise cancellation (DTC-MNC) technique is introduced, which adaptively measures and cancels error from DTC component mismatches using digital logic inserted between the phase-error-to-digital converter and the digital loop filter. This technique employs a background calibration method to ensure fast convergence and low jitter performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a DTC is implemented as a cascade of 1-bit DTC stages to achieve high linearity, then linearity is improved, but component mismatch error increases significantly
Solution Approach 1:
The patent applies dynamic element matching (DEM) to convert the harmful component mismatch error into highpass-shaped noise. By randomly switching between mismatched DTC components according to a pseudo-random sequence, the systematic mismatch error is transformed into stochastic noise with a highpass spectral shape, reducing its impact on in-band phase noise performance
Solution Approach 2:
The patent introduces dynamic switching of DTC components using DEM techniques. Instead of using fixed DTC components, the system dynamically switches between different components based on a pseudo-random sequence, making the DTC behavior time-varying and converting static mismatch errors into dynamic noise that can be filtered by the PLL loop
2Manufacturing precision
If analog techniques are used to linearize DTC circuits, then linearity is improved, but power consumption and circuit area increase considerably
Solution Approach 1:
The patent replaces analog linearization techniques with digital signal processing methods. Instead of using complex analog circuits to linearize the DTC, the system uses digital DEM encoding and background calibration algorithms to achieve linearization, thereby substituting analog complexity with digital processing
Solution Approach 2:
The patent changes the operating parameters of the DTC by applying background calibration that measures and compensates for DTC gain error and nonlinearity. The calibration process adjusts the DTC output based on measured parameters, enabling the DTC to operate accurately without requiring complex analog linearization circuits
3Manufacturing precision
If digital predistortion techniques are used to mitigate DTC nonlinearity, then linearity is improved, but convergence time becomes considerably longer than typical PLL settling times
Solution Approach 1:
The patent implements background calibration that operates continuously in the background during normal PLL operation. The calibration process performs preliminary measurement and compensation of DTC errors without waiting for the PLL to settle, enabling fast convergence that does not exceed typical PLL settling times
Solution Approach 2:
The patent maintains continuous calibration operation throughout PLL operation. The background calibration process continuously measures and compensates for DTC errors without interrupting the PLL's frequency synthesis function, ensuring that linearization is achieved and maintained throughout the entire operating period
Data Source
AI summary
A fractional-N PLL includes a reference oscillator, a multi-modulus divider-based phase-error-to-digital converter driven by the reference oscillator, a digital loop filter, and a digitally controlled oscillator. Digital-to-time to converter mismatch noise cancellation digital logic is between the phase-error-to-digital converter and the digital loop filter. Error from digital-to-time converter component mismatches is partially cancelled by the digital logic.