Dual-Tail PAM Sampler Timing to Reduce Kickback Noise
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Solution Overview
Problem
Pulse Amplitude Modulation (PAM) signal sampling in graphics processing units (GPUs) is prone to high kickback noise, which can cause signal distortion, timing errors, voltage spikes, and reduced system bit error rate (BER).
Innovation Solution
The use of dual-tail samplers with clock gating and asynchronous operation of multiple samplers reduces kickback noise. Specifically, dual-tail samplers include a first stage with an input pair, a cross-coupled load circuit, and a precharge device, along with pass-gate switches to control the sampling process. Additionally, the high, middle, and low dual-tail samplers operate at least partially asynchronously, with the high sampler operating on the rising edge of the clock and the middle and low samplers operating on the falling edge, or with clock gating based on the high sampler's output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple samplers operate simultaneously to sample PAM 4 signals, then sampling coverage is improved, but kickback noise increases
Solution Approach 1:
The patent implements periodic action by dividing the sampling operation into distinct clock phases. The high sampler operates during the first clock phase while the middle and low samplers are disabled, then the high sampler is disabled during the second clock phase while the middle and low samplers operate. This periodic activation pattern ensures complete sampling coverage across both clock phases while preventing all samplers from operating simultaneously, thereby reducing kickback noise.
2Productivity
If samplers operate continuously to maintain sampling speed, then productivity is improved, but power consumption increases
Solution Approach 1:
The patent applies periodic action by enabling samplers in alternating clock phases rather than continuously. The high sampler is enabled during the first clock phase and disabled during the second clock phase, while the middle and low samplers follow the opposite pattern. This periodic operation maintains continuous sampling capability across both phases while significantly reducing power consumption by keeping individual samplers inactive during their disabled phases.
Solution Approach 2:
The patent implements dynamics by dynamically controlling the enable/disable state of different samplers based on the current clock phase. The system transitions between different operational configurations: during the first clock phase, the high sampler is active while middle and low are inactive; during the second clock phase, the high sampler becomes inactive while middle and low become active. This dynamic reconfiguration optimizes both power consumption and sampling continuity.
Data Source
AI summary
The disclosed device can include a dual-tail sampler. The dual-tail sampler can include a first stage with an input pair, a cross-coupled load circuit, a precharge device between drain nodes of the input pair, and at least one pass-gate switch between the input pair and the cross-coupled load circuit. Various other devices and systems are also disclosed.