Analog Multiplexer Core Circuit for High-Speed Linear Signal Multiplexing
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Solution Overview
Problem
Existing analog multiplexer circuits face challenges in achieving high-speed and high-linearity time-multiplexing of analog signals due to limitations in switching speed and waveform distortion, particularly when handling large amplitude signals.
Innovation Solution
The proposed analog multiplexer core circuit employs a fully differential structure with emitter-coupled logic and strategically placed emitter resistors to ensure linear response, where the product of each emitter resistor and the current flowing through the constant current source is greater than or equal to the amplitude of the input analog signals, along with a differential amplifier for further signal processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If FET gating is used for analog signal switching, then linearity is improved, but switching speed becomes insufficient for high-speed operation
Solution Approach 1:
The patent replaces the mechanical FET gating system with an emitter-coupled logic system using bipolar transistors. This substitution enables high-speed operation (50 Gb/s or more) while maintaining signal linearity through the differential pair configuration and emitter coupling mechanism.
Solution Approach 2:
The patent changes the operating parameters by using bipolar transistors in a non-saturation region with emitter-coupled logic. This parameter change allows the circuit to achieve both high switching speed and good linearity simultaneously, resolving the contradiction between FET gating linearity and switching speed.
2Speed
If emitter-coupled logic is used for high-speed digital signal multiplexing, then switching speed is improved, but linearity deteriorates when handling analog signals
Solution Approach 1:
The patent introduces asymmetry in the circuit configuration by adding emitter resistors to the emitter-coupled logic circuit. This asymmetric modification (adding resistors to emitters) linearizes the transfer characteristics while preserving the high-speed switching capability of the original emitter-coupled structure.
Solution Approach 2:
The emitter resistors act as intermediaries between the bipolar transistors and the constant current source. These resistors provide negative feedback that linearizes the signal path, allowing the circuit to handle analog signals with good linearity while maintaining high-speed operation.
3Power
If the amplitude of input analog signals is increased, then signal strength is improved, but waveform distortion increases due to limited linear response range
Solution Approach 1:
The patent implements negative feedback through the emitter resistors connected to the emitters of the bipolar transistors. This feedback mechanism automatically adjusts the operating point to maintain linearity even when large amplitude signals are input, thereby reducing waveform distortion while preserving signal strength.
Solution Approach 2:
The emitter resistors provide beforehand cushioning by pre-establishing a linear operating region through negative feedback. This cushioning effect prevents the transistors from entering saturation or cutoff regions even when large amplitude signals are applied, thereby preventing waveform distortion before it occurs.
Data Source
AI summary
An analog multiplexer core circuit (120A) includes a differential pair (121) that includes two transistors (Q1, Q2), a differential pair (122) that includes two transistors (Q3, Q4), a differential pair (123) that includes two transistors (Q5, Q6), and a constant current source (124) that causes a current (IEE) to flow. This analog multiplexer core circuit (120A) time-multiplexes two analog signals (Ain1, Ain2) and outputs a time-multiplexed analog signal (Aout). Each emitter resistor (REA1, REA2, REA3, REA4) is connected to a corresponding one of the transistors (Q1, Q2, Q3, Q4). At this time, a relation of “REA·IEE≥the amplitude of an input analog signal” is satisfied. As a result, linearity of response can be ensured by expanding the linear response input range of the differential pairs (121, 122).