Transistor TRIZ Cases

Stacked double-MIM layers in deep trench capacitors raise capacitance density while voided insulation helps control wafer stress and warpage.

Ferroelectric transistor stacks merge memory and computing to cut data-transfer power while improving in-memory accuracy and speed.

Different-conductivity sections in a vertical transfer gate reshape the potential gradient to stop charge returning to the photodiode.

Charge-based gate voltage control raises saturation signal in global shutter pixels while suppressing dark current to widen dynamic range.

A light-shielding section blocks light from isolation-region charge storage layers, reducing blooming and color mixing in organic image sensors.

Multi-layer gate electrodes with work function metals and matching conductive layers cut resistance in vertical nanostructure channels while supporting scalable fabrication.

By replacing a sacrificial layer with buried bit lines, this memory structure increases density while preserving transistor channel length and performance.

Inclined platform surfaces and gate-insulator offsets extend conductive diffusion paths, preserving effective TFT channel length during downsizing.

A Widlar current mirror lets a low-power integrated high-side switch supply higher-power vehicle loads while still detecting overloads.

A stepped field insulating layer raises effective active fin height in scaled ICs, improving short-channel behavior and drive current.

Two regulated gate-drive paths let a DC-DC switch use the lower available supply, cutting external capacitors, size, and cost.

A cross-shaped localized isolation layout cuts CMOS leakage and latch-up while preserving channel conduction and reducing isolation area.

Conductive bars through insulator walls and trenches equalize base resistance in bipolar transistor rows, enabling denser phase-change memory arrays.

A surrounding gate and dual spacer layers improve short-channel control, hole mobility, and source-drain thickness uniformity.

An air-gap CPODE structure replaces dummy gates with low-k isolation to cut parasitic capacitance and RC delay in dense semiconductor layouts.

A thin contact region tuned by Schottky barrier height and doping lowers TFT contact resistance without worsening short channel effects.

On-grid dummy poly lines extend from active areas into isolation regions to cut CMP dishing and reclaim chip area at the 5 nm node.

A pump capacitor shifts the ground reference negative to keep cross-domain signal transfer correct and noise-robust at low floating supply voltages.

Using power rather than voltage to trigger startup, this circuit cuts solar energy waste and stops detection once the load is powered.

Merged fin pitch quartering uses spacer-defined patterning and isolation steps to achieve tighter fin spacing and higher transistor density.

Dividing the upper electrode in a photoelectric conversion pixel boosts phase-difference sensitivity for more accurate autofocus.

Vertical through-via routing links top and bottom interconnects while an air gap cuts coupling capacitance in multi-gate semiconductor structures.

Controlled terrace width and step height in a graphene-on-SiC stack reduce channel steps and improve transistor modulation stability.

Vertical stacking pairs a FinFET with a wraparound-gate nano FET to enlarge source/drain contact area and tighten electrostatic control.

A stepped dielectric fin and partial gate-stack removal create isolation regions that cut leakage and support reliable semiconductor scaling.

Segmented insulating regions and a common contact plug reduce leakage and recess defects while improving semiconductor yield.

A shallow channel and depletion-region pinching let one transistor switch between unipolar and bipolar conduction with improved gain and lower thresholds.

Alternating precursor and oxidizer cycles with oxygen-based impurity removal cut H, C, and N residues while improving metal oxide crystallinity.

A recessed pad in a vertical transistor enables self-aligned conductive contact formation while reducing corner damage, process complexity, and cost.

Vertically stacked channels with tiered recess depths extend effective channel length, suppress leakage, and improve MOSFET reliability.

An air-gap dielectric between the back gate and vertical channel cuts parasitic capacitance while enabling tighter semiconductor integration.

Spacer-defined polysilicon gates improve split-gate flash cell alignment, gate height control, and erase efficiency without extra masking steps.

A boundary region with lower p-type anode doping limits hole inflow into the diode region, cutting RC-IGBT recovery loss during switching.

Drain-bulk and gate-bulk fields generate secondary and tertiary electrons to program floating-gate memory with lower power and less oxide damage.

Two anti-series electronic switches protect DC loads from overcurrent in both directions while simplifying wiring and reducing losses.

A shared well lets one pickup bias multiple IC rows, saving layout space while maintaining effective latch-up protection.

Orthogonal conductive-line routing with different pitches is matched to CMOS fin circuits to raise memory density while saving semiconductor area.

A dielectric substrate under epitaxial source/drain regions cuts leakage and parasitic transistor formation in scaled multigate FETs.

A reduced gate fringe layout with shallow trench isolation improves surface breakdown voltage while avoiding complex LDD structures.

A backside trench and seal layer replace dielectric fins to increase gate separation and reduce parasitic coupling in dense multi-gate MOSFETs.

Hybrid oxide and silicon TFT pixels use overlapping capacitors to cut leakage, improve switching speed, and preserve display uniformity.

An oxide-nitride-imide passivation stack protects contact-electrode edges from humidity-driven corrosion while preserving voltage blocking.

A conformal protective layer balances polysilicon protection, silicide formation, and OTP leakage prevention by controlling thickness and residue removal.

Pseudo bit lines are removed before epitaxial regrowth of DRAM bit line contacts, avoiding etch damage and residual impurities.

Backside trenches etched through substrate and gate metal isolate nanosheet transistor gates without extra lithography, supporting higher density and yield.

HF/NH3 plasma-less pre-clean removes native oxide in FinFET recesses while protecting STI shape, reducing defects, and improving breakdown voltage.

A source-body resistor in a common-gate amplifier suppresses parasitic body capacitance, improving frequency response, dynamic range, and leakage.

A doped silicon interlayer with a germanium photodiode JFET reduces leakage current and raises optical fill factor for more reliable sensing.

Continuous active regions across adjacent standard cells and filler cells cut routing overhead, save area, and improve layout uniformity.

An upper-layer rail overlapping a buried power line keeps relay-cell supply continuous, easing standard-cell layout and stabilizing operation.