Semiconductor Memory Variable Capacitor Bit Line Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor memory devices face reliability degradation due to excessive electrical stress on transistors when using bit line potentials less than 0 V, leading to increased chip size and unnecessary voltage drops, especially at high power supply voltages.
Innovation Solution
The implementation of a semiconductor memory device with a variable capacitance capacitor and control circuits that adjust bit line potentials to lower values, using a power supply voltage detector to manage potential differences and reduce electrical stress, thereby optimizing the write operation at low power supply voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the bit line potential is caused to be smaller than 0 V to improve write operation at low power supply voltage, then the write characteristic is improved, but the electrical stress on the transistor increases and reliability degrades
Solution Approach 1:
The patent changes the voltage parameter dynamically by detecting the power supply voltage level and adjusting the bit line potential accordingly. When VDD is below the threshold, a negative potential is applied to improve write characteristic; when VDD is above the threshold, the bit line potential is maintained at 0 V or higher to prevent excessive electrical stress and ensure transistor reliability.
2Adaptability or versatility
If a negative potential generation circuit is designed to match a configuration having a great bit line length, then the chip size increases and excessive voltage drop occurs, but the negative potential generation capability is enhanced
Solution Approach 1:
The patent applies negative potential locally only to the selected bit line during write operations rather than generating excessive negative potential across the entire bit line network. The potential control is localized to where it is needed, preventing unnecessary voltage drops and reducing the required size of the negative potential generation circuit.
Solution Approach 2:
The patent dynamically controls the bit line potential based on real-time detection of power supply voltage levels and write operation status. The negative potential generation is activated only when needed (during write operations at low VDD) and deactivated when VDD is sufficient, making the potential generation capability adaptive rather than static.
3Manufacturing precision
If the bit line potential is excessively lowered to ensure write operation, then the write margin is improved, but the electrical stress accelerates element degradation
Solution Approach 1:
The patent employs a power supply voltage detector that provides feedback about the VDD level to the potential control circuit. This feedback mechanism ensures that negative potential is applied to the bit line only when VDD is below the predetermined threshold, maintaining adequate write margin while preventing excessive electrical stress that would accelerate element degradation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces or prevents reliability degradation of memory device elements while improving data write characteristics, minimizing chip size and electrical stress, even at high power supply voltages.
Implementation Method 1
a variable capacitance capacitor configured to control the potential of the selected bit line to a second potential which is lower than the first potential. The second potential is adjusted by a capacitance of the variable capacitance capacitor being changed, depending on a voltage applied to the variable capacitance capacitor
Data Source
AI summary
A semiconductor memory device includes a memory cell provided at an intersection of a word line and a bit line, a precharge circuit connected to the bit line, a column select circuit controlled in accordance with a write control signal, and a clamp circuit provided as a write circuit. The clamp circuit includes a transistor configured to control the potential of a selected bit line to a first potential (e.g., 0 V), and a variable capacitor configured to control the potential of the selected bit line to a second potential (e.g., a negative potential) which is lower than the first potential. The capacitance of the variable capacitor decreases when a power supply voltage is increased, whereby the amount of a decrease from the first potential to the second potential is reduced.