Stressed CMOS Channel Regions via Crystallographic Etching
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Solution Overview
Problem
Current semiconductor technologies face challenges in concurrently enhancing the performance of n-channel and p-channel FETs due to the difficulty in applying appropriate stresses, as compressive stress benefits p-FETs but adversely affects n-FETs, and vice versa, while existing stress-inducing materials can only enhance mobility in one type of FET, increasing processing complexity and cost.
Innovation Solution
The use of stressor layers with intrinsic compressive or tensile stress, positioned at acute or obtuse angles relative to the top surface, to apply different types of stress to the channel region of FETs, allowing the same material to induce both compressive and tensile stresses in n-FETs and p-FETs, respectively, by varying the orientation of additional surfaces in the semiconductor device structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different stress-inducing materials are used for p-FETs and n-FETs, then mobility enhancement for both FET types is achieved, but processing complexity and cost increase
Solution Approach 1:
The patent employs the same stressor material (such as SiGe or Si:C) for both p-FET and n-FET stress induction. The universality is achieved by varying the orientation of additional surfaces and the configuration of stressor layers rather than using different materials. This approach maintains processing simplicity while achieving the differential stress requirements for both FET types.
Solution Approach 2:
Instead of changing materials, the patent changes geometric parameters to achieve different stress effects. The orientation angles of additional surfaces relative to the top surface are varied (first angles for p-FETs, second angles for n-FETs), and the thicknesses and positions of stressor layers are adjusted. These parameter changes enable the same material to provide different stress types to different FET regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables simultaneous enhancement of electron and hole mobility in both n-FETs and p-FETs using the same stressor materials, reducing processing complexity and costs by eliminating the need for additional processing steps.
Implementation Method 1
methods for forming the FET by crystallographic etching and pseudomorphic growth of stressor layers
Implementation Method 2
mechanical stresses within a semiconductor device substrate can also be used to modulate device performance
Data Source
AI summary
The present invention relates to improved complementary metal-oxide-semiconductor (CMOS) devices with stressed channel regions. Specifically, each improved CMOS device comprises an field effect transistor (FET) having a channel region located in a semiconductor device structure, which has a top surface oriented along one of a first set of equivalent crystal planes and one or more additional surfaces oriented along a second, different set of equivalent crystal planes. Such additional surfaces can be readily formed by crystallographic etching. Further, one or more stressor layers with intrinsic compressive or tensile stress are located over the additional surfaces of the semiconductor device structure and are arranged and constructed to apply tensile or compressive stress to the channel region of the FET. Such stressor layers can be formed by pseudomorphic growth of a semiconductor material having a lattice constant different from the semiconductor device structure.