Level Shift Circuit With Precharge for Stable Clock Duty
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Solution Overview
Problem
The existing level shift circuits face issues with unstable potential at node N2, leading to variations in the duty of the output clock, which can result in reduced H-pulse width and insufficient setup or holding time for data latching, causing incorrect data values due to rapid changes in signal levels.
Innovation Solution
A charging circuit is introduced to stabilize the potential at node N2 by connecting a switch between the power-supply potential and node N2, ensuring immediate charging before data transitions, thereby improving the duty of the output clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional level shift circuit is used, then signal level conversion is achieved, but the potential at node N2 becomes unstable causing duty cycle variations
Solution Approach 1:
The charging circuit charges node N2 in advance before the data signal transitions, ensuring that the node reaches a stable potential state before the critical latching operation occurs. This preliminary charging action prevents duty cycle variations and ensures reliable signal level conversion.
Solution Approach 2:
The charging circuit acts as an intermediary component between the power supply and node N2, providing controlled charging current to stabilize the node potential. This intermediary element isolates the instability source while maintaining the necessary voltage level for reliable operation.
2Productivity
If the potential at node N2 varies, then the output clock duty changes, but the H-pulse width becomes insufficient for proper data latching
Solution Approach 1:
The charging circuit performs preliminary charging of node N2 before the data transition occurs, ensuring that the output clock maintains adequate H-pulse width. This advance preparation prevents insufficient setup and holding times, enabling precise data latching while maintaining high transmission speed.
3Speed
If signal levels change rapidly, then transmission speed is improved, but incorrect data values occur due to insufficient latching time
Solution Approach 1:
By charging node N2 in advance before rapid signal transitions, the charging circuit ensures that the output clock has sufficient H-pulse width even during high-speed operation. This preliminary action maintains data latching accuracy while preserving fast transmission speeds.
Solution Approach 2:
The charging circuit provides a cushioning effect by pre-charging node N2, creating a buffer that protects against the harmful effects of rapid signal changes. This beforehand cushioning ensures adequate latching time is maintained even during high-speed transitions, preventing incorrect data values.
Data Source
AI summary
According to one embodiment, in a level shift circuit, a first PMOS transistor is electrically connected at a gate to a first node to which a first signal having an amplitude to be a first power-supply potential is input, is electrically connected to a second node at a source, and is electrically connected at a drain to an output terminal from which a signal having an amplitude to be a second power-supply potential is output. The first NMOS transistor is electrically connected to the first node at a gate and is electrically connected to the output terminal at a drain. The second PMOS transistor is electrically connected to a node to be the second power-supply potential at a source, and is electrically connected to the second node at a drain. The potential adjusting circuit is electrically connected to at least the second node.