Doped Amorphous Silicon Layer for Array Substrate Leakage
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Solution Overview
Problem
Thin film transistors in liquid crystal displays are prone to image sticking due to polarization of liquid crystal molecules over time, caused by leakage in the array substrate, leading to persistent still images on the screen.
Innovation Solution
A method and device for manufacturing an array substrate that involves depositing and forming a gate insulation layer, an amorphous silicon layer, a doped amorphous silicon layer with increasing doping concentrations, and a metal layer, followed by etching patterns and forming a passivation layer, which enhances the energy barrier and reduces leakage current, thereby improving the stability of the thin film transistor array substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional single-layer amorphous silicon structure is used, then the manufacturing process is simple, but the leakage current is high causing image sticking
Solution Approach 1:
The amorphous silicon layer is segmented into multiple sub-layers with different doping concentrations (first doped amorphous silicon layer, second doped amorphous silicon layer, third doped amorphous silicon layer). This segmentation creates a multi-layered energy barrier structure that more effectively prevents leakage current compared to a single-layer structure, while maintaining manageable manufacturing complexity through systematic doping concentration gradients.
Solution Approach 2:
Different regions of the amorphous silicon structure are assigned different doping concentrations to create locally optimized properties. The first doped amorphous silicon layer has a first doping concentration, the second has a second doping concentration higher than the first, and the third has a third doping concentration higher than the second. This local quality variation creates an energy barrier that specifically targets leakage current paths without affecting other regions uniformly.
2Reliability
If the doping concentration is uniformly high throughout the amorphous silicon layer, then the energy barrier is high, but the manufacturing precision is difficult to control
Solution Approach 1:
The amorphous silicon layer is divided into multiple segments (first, second, and third doped amorphous silicon layers) with progressively increasing doping concentrations. This segmentation allows each layer to be manufactured within controllable doping ranges while collectively achieving a high overall energy barrier, avoiding the difficulty of manufacturing a single layer with uniformly high and precise doping concentration.
Solution Approach 2:
The doping concentration parameter is changed progressively across different layers rather than being uniformly applied. The first doped amorphous silicon layer has a first doping concentration, the second has a second doping concentration higher than the first, and the third has a third doping concentration higher than the second. This parameter progression allows for better manufacturing control at each stage while achieving the desired high energy barrier effect.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces leakage current and enhances the stability of the array substrate, preventing image sticking issues in thin film transistors by increasing the energy barrier through the use of doped amorphous silicon layers with gradually increasing doping concentrations.
Implementation Method 1
a doped amorphous silicon layer provided on the amorphous silicon layer and including at least three doped layers, doping concentrations of the at least three doped layers of the doped amorphous silicon layer increasing from bottom to top
Implementation Method 2
increases the energy barrier, thereby reducing the leakage current
Implementation Method 3
depositing and forming a gate insulation layer on a pre-formed base substrate and a pre-formed gate, the gate insulation layer covering the pre-formed gate
Implementation Method 4
forming a passivation layer covering the patterns of the amorphous silicon layer, the doped amorphous silicon layer and the metal layer
Data Source
AI summary
Disclosed are a method and a device for manufacturing an array substrate, and an array substrate. The method includes: depositing and forming a gate insulation layer on a pre-formed base substrate and a pre-formed gate, the gate insulation layer covering the pre-formed gate; depositing and forming an amorphous silicon layer, a doped amorphous silicon layer including at least three doped layers, and a metal layer on the gate insulation layer in sequence, doping concentrations of the at least three doped layers of the doped amorphous silicon layer increasing from bottom to top; etching patterns of the amorphous silicon layer, the doped amorphous silicon layer and the metal layer to form the array substrate.