Embedded Power Stage FET Interconnect via Conductive Vias
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Solution Overview
Problem
Existing power converter designs face inefficiencies due to high electrical resistance in bonding wires and limited flexibility in solder bump-based interconnects, leading to increased power losses and heat generation in stacked integrated circuits.
Innovation Solution
A power stage module is embedded in a laminated dielectric substrate with conductive vias and foil layers, allowing for precise and dense electrical interconnects between high side and low side FETs, reducing power losses and heat generation by using laser-drilled and electroplated vias and etched metallic foils.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If bonding wires are used to connect FETs to leadframe, then electrical connections can be established, but electrical resistance is high leading to power losses
Solution Approach 1:
The patent extracts the FETs from traditional leadframe mounting and embeds them directly into the PCB substrate. This eliminates the need for bonding wires connecting FETs to leadframe, thereby removing the source of high electrical resistance and associated power losses while maintaining reliable electrical connections through direct substrate integration.
Solution Approach 2:
The patent introduces conductive vias as intermediary elements to establish electrical connections between embedded FETs and external circuitry. These vias provide low-resistance conductive paths through the substrate, replacing the high-resistance bonding wire connections while maintaining the necessary electrical connectivity.
2Adaptability or versatility
If solder bumps are used for flip chip-style connections, then FETs can be connected to leadframe, but flexibility in interconnect design is limited
Solution Approach 1:
The PCB substrate serves multiple functions simultaneously: it provides mechanical support, electrical connectivity through conductive vias, thermal management pathways, and design flexibility. This multi-functional integration eliminates the need for separate leadframe and solder bump interconnect structures, enabling greater design adaptability while simplifying the overall manufacturing process.
Solution Approach 2:
The patent merges the leadframe function with the PCB substrate by embedding FETs directly into the substrate and using conductive vias for interconnects. This consolidation eliminates the separate leadframe component and solder bump interconnect layer, providing greater design flexibility while reducing manufacturing steps and assembly complexity.
3Power
If stacked FET configuration is used, then power conversion function is achieved, but heat generation increases due to power losses
Solution Approach 1:
The patent extracts FETs from traditional high-resistance bonding wire connections and embeds them directly into the PCB substrate with low-resistance conductive vias. This removal of high-resistance interconnect elements reduces I²R power losses during power conversion operations, thereby decreasing heat generation while maintaining full power conversion capability.
Solution Approach 2:
The patent introduces conductive vias as intermediary elements that provide low-resistance electrical paths between embedded FETs and external circuitry. These vias minimize electrical resistance and associated power losses during power conversion, thereby reducing heat generation while enabling effective power conversion functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances power density and flexibility in electrical interconnect design, reducing power losses and heat generation within the package while avoiding the limitations of traditional bonding wires and solder bumps.
Implementation Method 1
Metal is electroplated into the holes to form electrically conductive vias
Implementation Method 2
The holes may be formed, for example, using a laser
Implementation Method 3
A power stage module is embedded in a laminated dielectric substrate
Data Source
AI summary
One aspect of the invention pertains to an integrated circuit package with an embedded power stage. The integrated circuit package includes a first field effect transistor (FET) and a second FET that are electrically coupled with one another. The FETs are embedded in a dielectric substrate that is formed from multiple dielectric layers. The dielectric layers are laminated together with one or more foil layers that help form an electrical interconnect for the package. Various embodiments relate to method of forming the above package.