Analog Switch Gate Modulation for Lower Off-State GIDL
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Solution Overview
Problem
Existing CMOS switches suffer from significant gate-induced drain leakage (GIDL) current when in the off-state, which affects the performance of systems utilizing multiple switches, particularly in analog applications where combined leakage currents can impact performance.
Innovation Solution
An analog switch design featuring NMOS and PMOS circuits in parallel, with buffer transistors and a control circuit that applies modulated gate voltages alternating between supply voltage and GIDL mitigation voltage based on switch state to reduce GIDL current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional CMOS switches are used in off-state, then the device structure is simple, but gate-induced drain leakage current is significant
Solution Approach 1:
The patent segments the single transistor structure into two separate transistors (first transistor and second transistor) with their sources connected together. This segmentation allows independent control of gate voltages to mitigate GIDL current while maintaining the basic switch functionality, resolving the contradiction between structural simplicity and leakage reduction.
Solution Approach 2:
The patent changes the voltage parameters applied to the gates of the two transistors. By applying different voltages to the first and second gates independently, the patent optimizes the electric field distribution to reduce GIDL current. This parameter change approach allows leakage reduction without significantly complicating the device structure.
2Adaptability or versatility
If multiple CMOS switches are coupled to a common terminal, then the system functionality is enhanced, but combined leakage current scales and significantly impacts performance
Solution Approach 1:
By segmenting each switch into two transistors with independent gate control, the patent enables individual optimization of leakage current for each switch. When multiple switches are coupled to a common terminal, this segmentation allows each switch to independently minimize its leakage contribution, preventing the combined leakage from scaling proportionally with the number of switches.
3Object-generated harmful factors
If buffer transistors are added to reduce GIDL current, then leakage current is reduced, but device complexity increases
Solution Approach 1:
The patent makes the two transistors serve multiple functions: they act as the primary switching elements while simultaneously functioning as leakage mitigation devices through their coordinated operation. This multi-functionality approach reduces leakage current without adding separate buffer transistor structures, thereby avoiding excessive complexity increase.
Data Source
Figure 1A~1B
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AI summary
In an example, an apparatus includes an analog switch (102) having an n-type metal oxide semiconductor (NMOS) circuit (202) in parallel with a p-type metal oxide semiconductor (PMOS) circuit (204) between a switch input and a switch output. The analog switch (102) is responsive to an enable signal that determines switch state thereof. The NMOS circuit (202) includes a switch N- channel transistor coupled to a buffer N-channel transistor, a gate of the switch N-channel transistor coupled to the enable signal and a gate of the buffer N- channel transistor coupled to a modulated N-channel gate voltage. The PMOS circuit (204) including a switch P-channel transistor coupled to a buffer P- channel transistor, a gate of the switch P-channel transistor coupled to a complement of the enable signal and a gate of the buffer P-channel transistor coupled to a modulated P-channel gate voltage. A control circuit (208) is coupled to the analog switch (102) to provide the modulated N-channel and modulated P-channel gate voltages each of which alternates between a respective supply voltage and a respective gate induced drain leakage (GIDL) mitigation voltage based on the switch state.