Thin-Film Transistor Array Structure for Effective Channel Length Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The diffusion of electrically conductive effects on both ends of the channel in conventional thin-film transistor devices leads to low-resistance regions, resulting in a shorter effective channel length, which hinders the downsizing of thin-film transistor devices.
Innovation Solution
A thin-film transistor array substrate design featuring a platform layer with inclined end surfaces and a gate insulating layer with offset portions, which extends the conductive diffusion path and reduces the length of low-resistance regions formed through self-aligned etching, ensuring an effective channel length suitable for downsizing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If self-aligned etching processes are used to reduce resistance outside channels, then resistance reduction is achieved, but effective channel length becomes shorter
Solution Approach 1:
The patent introduces a vertical dimension by forming the active layer on an inclined platform layer, creating different vertical levels for the channel portion versus the conductor portions. This vertical offset prevents horizontal diffusion of conductive effects from contaminating the channel region, thus maintaining effective channel length while still achieving resistance reduction through controlled conductive paths at the conductor portions.
Solution Approach 2:
The active layer is designed with different local properties: the channel portion remains non-conductive with higher resistance to maintain effective length, while the conductor portions are made conductive with lower resistance. The inclined platform layer creates distinct zones where conductive effects are localized to specific regions (conductor portions) rather than diffusing uniformly, allowing each region to have optimized electrical characteristics for its function.
2Reliability
If conductor portions are made conductive through diffusion, then resistance at ends of channel is reduced, but diffusion extends into channel portion shortening effective length
Solution Approach 1:
By creating a vertical offset between the channel portion and conductor portions through the inclined platform layer, the patent establishes a spatial barrier that prevents lateral diffusion of conductive effects from the conductor portions into the channel portion. The conductive diffusion is confined to the conductor portions at the lower vertical level, while the channel portion at the higher vertical level remains protected, thus maintaining effective channel length.
Solution Approach 2:
The inclined platform layer acts as an intermediary structure that mediates between the conductor portions and the channel portion. It provides a geometric configuration where the offset portions of the gate insulating layer and the slopes of the platform layer create a physical barrier that controls and limits the diffusion path of conductive effects, allowing them to reach the conductor portions without invading the channel region.
3Manufacturing precision
If gate patterns are formed simultaneously with gate insulating layer etching, then alignment deviation is prevented, but conductive effect diffusion still occurs at channel ends
Solution Approach 1:
The patent applies local quality by creating offset portions of the gate insulating layer that extend beyond the gate electrode at specific locations. These offset portions are strategically positioned to provide additional coverage over the conductor portions during etching, creating a localized protective barrier that prevents conductive effect diffusion into the channel region while maintaining precise gate alignment.
Solution Approach 2:
The solution moves from a two-dimensional planar approach to a three-dimensional structure with vertical offsets. The gate insulating layer is formed with offset portions that create a vertical and horizontal barrier, and the inclined platform layer establishes different vertical levels. This dimensional change provides an additional protective dimension that prevents diffusion even when gate patterns are formed simultaneously with etching.
Data Source
AI summary
A thin-film transistor array substrate and a method of manufacturing the same are disclosed. The thin-film transistor array substrate includes a substrate and a platform layer disposed on the substrate. An oxide active layer includes a channel portion and two conductor portions. A source electrode and a drain electrode are electrically connected to the conductor portions. A vertical level of a top surface of the channel portion is higher than a vertical level of a top surface of any one of the conductor portions. An orthographic projection of a gate electrode on the substrate covers orthographic projections of the platform layer and the channel portion on the substrate.