On-SOI Triac ESD Protection Circuit
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Solution Overview
Problem
Integrated circuits produced using FDSOI technology face challenges in achieving distinct threshold voltages for transistors, which is crucial for balancing low power consumption and high toggling speed, while existing solutions are technically complex and economically prohibitive.
Innovation Solution
The use of buried insulating layers, doped ground planes, and shallow isolation trenches to modulate threshold voltages and integrate ESD protection devices that are compact, efficient, and inexpensive, ensuring protection against electrostatic discharges without compromising integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different gate materials are integrated to produce transistors with distinct threshold voltages, then transistors with low threshold voltage (LVT) and high threshold voltage (HVT) can be achieved, but the production becomes technically complex and economically prohibitive
Solution Approach 1:
The patent changes the physical state and properties of the ground plane by introducing controlled doping (changing concentration and type of dopants) and applying electrical bias, rather than changing gate materials. This allows threshold voltage modulation through parameter adjustment of existing structures, avoiding the complexity of integrating different gate materials while achieving the same functional result of distinct threshold voltages
2Reliability
If isolation trenches are extended deep to electrically insulate transistors, then electrical insulation is achieved, but the integration density is reduced and the circuit compactness is compromised
Solution Approach 1:
The patent merges the isolation function with the ground plane structure by making the ground plane extend into the isolation trench and form an integrated structure. The ground plane serves dual purposes: providing electrical reference potential and providing isolation when combined with the buried oxide layer, eliminating the need for deep isolation trenches while maintaining both insulation and compactness
3Reliability
If ESD protection devices are integrated into the circuit, then protection against electrostatic discharges is provided, but the circuit compactness is reduced
Solution Approach 1:
The patent makes the ground plane and isolation structure serve multiple functions simultaneously: electrical reference, transistor isolation, and ESD protection. The doped ground plane with appropriate bias can detect and respond to ESD events while maintaining its primary functions, eliminating the need for separate dedicated ESD protection structures and thus preserving circuit compactness
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the production of integrated circuits with distinct threshold voltages, enhancing both low power consumption and high toggling speed while providing effective and localized protection against electrostatic discharges, maintaining circuit compactness and reducing costs.
Implementation Method 1
By altering the doping of the ground planes and their bias, it is possible to define a range of threshold voltages for the different transistors
Implementation Method 2
The integrated circuit also includes a device for protection against accidental electrostatic discharges
Data Source
AI summary
An integrated circuit includes four electronic components, a buried UTBOX layer under and plumb with the electronic components, and two pairs of oppositely doped ground planes plumb with corresponding components under the layer. A first isolation trench mutually isolates the ground planes from corresponding wells made plumb and in contact with the ground planes and exhibiting the first doping type. Bias electrodes contact respective wells and ground planes. One pair of electrodes is for connecting to a first bias voltage and the other pair is for connecting to a second bias voltage. Also included are a semiconductor substrate exhibiting the first type of doping and a deeply buried well exhibiting the second type of doping. The deeply buried well contacts the other wells and separates them from the substrate. Finally, a control electrode couples to the deeply buried well.