Ferroelectric Neuromorphic Transistor Stack for Accurate In-Memory Computing
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Solution Overview
Problem
The Von Neumann computing architecture limits energy efficiency and processing speed for large data sets due to inefficient data transfer between main memory and CPU, and existing in-memory computing technologies using RRAM or PCM suffer from accuracy issues due to asymmetric and nonlinear weight changes.
Innovation Solution
The development of semiconductor devices and neuromorphic circuits incorporating ferroelectric materials, which enable efficient data processing by simulating synaptic functions, allowing for parallel processing and improved data storage and retrieval, thereby enhancing the accuracy and speed of data processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If Von Neumann architecture with separate main memory and CPU is used, then device structure is simple and ease of manufacture is improved, but data transfer efficiency deteriorates and power consumption increases
Solution Approach 1:
The patent merges memory and computing functions into a single integrated device structure. The ferroelectric transistor stack combines storage (ferroelectric layer) and logic (transistor) functions, eliminating the need for separate memory and CPU components. This integration reduces data transfer distances and enables in-memory computing, directly addressing the energy efficiency problem while maintaining manufacturing feasibility through standardized semiconductor fabrication processes.
Solution Approach 2:
The ferroelectric transistor serves multiple functions simultaneously: it acts as both a memory element (storing data in the ferroelectric layer) and a logic element (performing computations through transistor operation). This multi-functionality allows the same physical structure to handle both storage and processing tasks, reducing the need for separate dedicated components and improving overall system efficiency.
2Device complexity
If Von Neumann architecture with sequential data processing is used, then device structure is simple, but processing speed deteriorates for large data sets
Solution Approach 1:
The patent transitions from planar 2D transistor structures to vertically stacked 3D architectures. The multi-layer stack configuration allows multiple computational and storage elements to be integrated in the vertical dimension, enabling parallel processing operations without increasing lateral device footprint. This dimensional transition facilitates higher processing speeds while maintaining manageable device complexity.
3Speed
If RRAM or PCM is used for in-memory computing, then processing speed is improved, but measurement precision deteriorates due to asymmetric and nonlinear weight changes
Solution Approach 1:
The patent changes the fundamental material parameter from resistive switching materials (RRAM/PCM) to ferroelectric materials. This parameter change enables linear and symmetric weight adjustments in the synaptic connections, improving measurement precision for neural network computations while maintaining high processing speeds through fast ferroelectric switching characteristics.
Solution Approach 2:
The device employs a composite structure combining ferroelectric materials with conventional semiconductor materials. This composite approach leverages the non-volatile memory properties and fast switching of ferroelectrics while maintaining compatibility with standard semiconductor fabrication, achieving both high speed and high precision simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution achieves high accuracy in image recognition tasks, with a 97.3% identification rate on the MNIST dataset, significantly outperforming traditional technologies, while reducing power consumption and improving processing speed.
Implementation Method 1
The gate insulating film includes a ferroelectric material
Data Source
AI summary
A semiconductor device includes a first transistor including a first channel layer of a first conductivity type, a second transistor provided in parallel with the first transistor and including a second channel layer of a second conductivity type, and a third transistor stacked on the first and second transistors. The third transistor may include a gate insulating film including a ferroelectric material. The third transistor may include third channel layer and a gate electrode that are spaced apart from each other in a thickness direction with the gate insulating film therebetween.