Vertical Channel Device Etching Profile Control
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Solution Overview
Problem
Forming vertical channel devices with good electrostatic properties and low series resistance is challenging due to the adverse impact of thin channel dimensions on series resistance and wide channel dimensions on electrostatics.
Innovation Solution
A method involving the etching of a semiconductor layer stack with different materials for the upper, intermediate, and lower layers, using distinct etching chemistries to control the profile, where the etching chemistry is changed upon reaching the lower layer to form a lower portion with a gradually increasing lateral dimension, thereby increasing the contact area and improving electrostatics and series resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thin channel is formed to improve electrostatic properties, then electrostatic control is improved, but series resistance increases
Solution Approach 1:
The patent applies local quality by creating different lateral dimensions at different vertical locations of the channel. The channel has a first lateral dimension in the upper portion and a second lateral dimension in the lower portion, allowing the upper channel to maintain small dimensions for good electrostatic control while the lower channel expands to reduce series resistance at the contact region.
2Object-affected harmful factors
If a wide lower source/drain portion is formed to reduce series resistance, then series resistance decreases, but channel width increases adversely affecting electrostatics
Solution Approach 1:
The invention resolves this contradiction by making the channel width location-dependent. The channel maintains a first lateral dimension (narrower) in the upper portion where electrostatic control is critical, and transitions to a second lateral dimension (wider) in the lower portion where contact area and series resistance are the dominant concerns.
Solution Approach 2:
The patent introduces a vertical dimension to the channel width variation, creating a three-dimensional channel structure where the lateral dimension changes along the vertical axis. This allows independent optimization of electrostatics (upper portion) and series resistance (lower portion) by exploiting the additional vertical degree of freedom.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enables the formation of vertical channel devices with targeted lateral dimensions, achieving improved electrostatic properties and reduced series resistance by controlling the etching process and using specific fluoride-to-carbon ratios in etching chemistries.
Implementation Method 1
Legtenberg et al., in 'Anisotropic Reactive Ion Etching of Silicon Using SF6/O2/CHF3', J. Electrochem. Soc., Vol 142 (1995), No. 6, pages 2020-2028 describes the use of fluorine-, oxygen- and carbon-containing gas in etching tapered profiles in silicon.
Implementation Method 2
the modified etching chemistry is such that the lower portion is formed to present, along at least a part of said lower portion, a lateral dimension gradually increasing along a direction towards the substrate
Data Source
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AI summary
According to an aspect of the present inventive concept there is provided a method for forming a vertical channel device, the method comprising: forming a vertical semiconductor structure including an upper portion, an intermediate portion and a lower portion, by etching a semiconductor layer stack arranged on a substrate, the semiconductor layer stack including an upper semiconductor layer, an intermediate semiconductor layer and a lower semiconductor layer, wherein the intermediate semiconductor layer is formed of a material different from a material of the lower semiconductor layer and different from a material of the upper semiconductor layer, wherein the forming of the vertical semiconductor structure comprises: etching the upper semiconductor layer to form said upper portion and the intermediate semiconductor layer to form said intermediate portion, detecting whether said etching has reached the lower semiconductor layer, and in response to detecting that said etching has reached the lower semiconductor layer, changing to a modified etching chemistry being different from an etching chemistry used during said etching of the intermediate semiconductor layer, and etching the lower semiconductor layer using the modified etching chemistry to form said lower portion, wherein the modified etching chemistry is such that the lower portion is formed to present, along at least a part of said lower portion, a lateral dimension gradually increasing along a direction towards the substrate, and the method further comprising: forming a gate stack extending vertically along the intermediate portion to define a channel region of the vertical channel device.