Vertical Memory Structure Using Buried Bit Lines for Higher Density
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Solution Overview
Problem
The challenge is to increase the storage density of memory without reducing the performance of transistors, which is hindered by the narrow channel and short channel effects as the size of planar transistors is decreased.
Innovation Solution
A method is developed to form a semiconductor structure with a vertical transistor and a buried bit line, where the sacrificial layer is replaced by the bit line, allowing for a smaller layout size and increased integration density without decreasing the channel length, facilitating the formation of a vertical transistor array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the channel size of planar transistors is reduced to decrease transistor size, then the storage density of memory is increased, but the narrow channel effect and short channel effect lead to degradation of transistor performance
Solution Approach 1:
The patent transitions from planar transistors to vertical transistors, changing the dimensional orientation of the channel from horizontal to vertical. This allows the channel length to be determined by the thickness of the active layer rather than lateral dimensions, enabling smaller footprint while maintaining adequate channel length for performance
2Productivity
If the channel size of planar transistors is reduced to increase storage density, then more transistors can be integrated, but the narrow channel and short channel effects restrict further improvement
Solution Approach 1:
By forming vertical transistors with the channel extending vertically through the active layer thickness, the patent achieves better control over channel length independent of the lateral footprint. This allows higher integration density without the performance degradation caused by short channel effects in planar devices
Solution Approach 2:
The patent changes the critical parameter from lateral channel dimensions to vertical active layer thickness to define channel length. This parameter change enables decoupling of channel length control from device footprint, allowing optimization of both performance and density
Data Source
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AI summary
This application relates to a semiconductor structure and a forming method therefor, and a memory and a forming method therefor. The method for forming the semiconductor structure includes: providing a substrate, forming a sacrificial layer and an active layer on the sacrificial layer on the substrate; etching the active layer and the sacrificial layer to form active lines extending along a first direction; forming a first isolation layer that fills a spacing between the active lines; etching ends of the active lines to form openings, and exposing the sacrificial layer on side walls of the openings; removing the sacrificial layer along the openings, and forming gaps between a bottom of the active lines and the substrate; and filling the gaps with a conductive material to form bit lines extending along the first direction. The method for forming the semiconductor structure is conducive to improving integration density and performance of transistors, thereby increasing a memory storage density.