Parallel NMOS and bigFET ESD Protection for High Peak Current
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Solution Overview
Problem
Conventional ESD protection devices are inadequate in handling system-level ESD pulses with high peak currents, risking physical damage to the device and the protected circuit due to their design for lower peak currents.
Innovation Solution
An ESD protection device comprising an NMOS transistor and a bigFET connected in parallel, where the NMOS transistor shunts the first peak of the ESD pulse and the bigFET handles the second peak, with a trigger device and decoupling capacitor to manage the current effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional ESD protection device is used, then it can protect against regular ESD pulses with low peak current, but it cannot handle system-level ESD pulses with high peak current without risking physical damage
Solution Approach 1:
The ESD protection function is segmented into two distinct transistors: a first transistor (conventional ESD protection type) that handles regular ESD pulses with low peak current, and a second transistor (bigFET type) that handles system-level ESD pulses with high peak current. Each transistor is optimized for its specific current range, allowing the system to reliably protect against both types of ESD events without risking physical damage to either component.
2Reliability
If the ESD protection device is designed for high peak current, then it can handle system-level ESD pulses, but it increases device complexity and may not provide optimal protection for regular ESD pulses
Solution Approach 1:
Rather than designing a single complex transistor to handle all ESD scenarios, the protection device is segmented into two specialized transistors connected in parallel. This segmentation allows each transistor to be optimized for its specific function while keeping individual component complexity manageable. The first transistor handles regular ESD pulses efficiently, while the second transistor provides the necessary current handling capability for system-level events.
Solution Approach 2:
The ESD protection device achieves multi-functionality by combining two different transistor types in parallel. The first transistor provides optimal protection for regular ESD pulses, while the second transistor provides backup capacity for system-level ESD pulses. This universal design allows a single protection device to handle multiple types of ESD events effectively.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively protects against both regular and system-level ESD pulses by distributing the current peaks across the NMOS transistor and bigFET, preventing damage and ensuring reliable operation.
Implementation Method 1
an ESD protection device can be integrated into an integrated circuit (IC) chip to provide a low impedance channel to ground to protect against thermal damage
Implementation Method 2
The gate terminal and the body of the NMOS transistor are connected to the source terminal via a resistor
Implementation Method 3
the ESD protection device further includes a decoupling capacitor connected in parallel with the NMOS transistor
Data Source
AI summary
Embodiments of an electrostatic discharge (ESD) protection device and a method of operating an ESD protection device are described. In one embodiment, an ESD protection device includes an NMOS transistor configured to shunt current in response to an ESD pulse and a bigFET connected in parallel with the NMOS transistor. The NMOS transistor includes a source terminal, a gate terminal, and a body. The gate terminal and the body of the NMOS transistor are connected to the source terminal via a resistor. Other embodiments are also described.