Bootstrap Clock Step-Up Circuit for Sampling Switch Reliability
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Solution Overview
Problem
High-level clock voltage generated by existing clock voltage step-up circuits can lead to reliability issues when dealing with large voltage ranges of signals to be sampled, necessitating a solution to limit the step-up amplitude of the control signal voltage to prevent excessive voltage at circuit nodes.
Innovation Solution
A clock voltage step-up circuit comprising a first inverter, a second inverter, a third inverter, a PMOS transistor, and a bootstrap capacitor, utilizing two-phase non-overlapping clock signals to generate control signals for sampling switches, effectively stepping up the voltage while avoiding excessive voltage at circuit nodes, and employing conventional CMOS process components for simplicity and cost-effectiveness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the voltage of the control signal is increased to reduce on-resistance and improve switching speed, then the switching performance is improved, but the reliability of the circuit deteriorates due to excessive voltage at circuit nodes
Solution Approach 1:
The circuit dynamically adjusts the control signal voltage level based on the input signal voltage range. When the input signal voltage range is small, the control signal voltage is increased to improve switching speed. When the input signal voltage range is large, the control signal voltage is limited to prevent excessive voltage at circuit nodes, thus maintaining reliability.
Solution Approach 2:
The circuit changes the voltage parameter of the control signal adaptively. By detecting the voltage range of the input signal, the circuit adjusts the step-up amplitude of the control signal voltage, transforming a fixed voltage approach into a variable voltage approach that optimizes both speed and reliability under different operating conditions.
2Ease of manufacture
If conventional CMOS process components are used to simplify the structure and reduce cost, then manufacturing cost is reduced, but the ability to handle large voltage ranges deteriorates
Solution Approach 1:
The circuit uses dynamic voltage adjustment to handle different voltage ranges. By adaptively changing the control signal voltage level based on the input signal characteristics, the circuit maintains versatility in handling various voltage ranges while using only conventional CMOS components, avoiding the need for specialized high-voltage processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed circuit improves reliability by preventing excessive voltage, reduces layout area, and operates with a simple, flexible structure, using conventional CMOS components to avoid high-cost processes and minimize masks, while allowing operation at low clock frequencies.
Implementation Method 1
a bootstrap capacitor, an end of the bootstrap capacitor being connected to an output end of the third inverter, and another end of the bootstrap capacitor being connected to a drain end of the PMOS transistor and being connected to the second inverter, to step up the voltage of the clock signal output by the output end of the second inverter
Data Source
AI summary
A clock voltage step-up circuit comprises a first inverter, a second inverter, a third inverter, a PMOS transistor, and a bootstrap capacitor. An input end of the first inverter is used for inputting a first clock signal. An input end of the second inverter is connected to an output end of the first inverter, and an output end of the second inverter outputs a first control signal used for controlling a sampling switch; and after the first control signal passes through a fourth inverter, a fifth inverter and a sixth inverter, a second control signal used for controlling the sampling switch is generated. An input end of the third inverter is connected to a second clock signal, and the first clock signals and the second clock signals are a set of clock signals, every two of which are not overlapped.