Segmented Word Line Thermal Annealing for Flash Memory Endurance
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Solution Overview
Problem
Flash memory technologies face challenges in improving the speed of operation and endurance due to performance degradation from accumulated defects and trapped charges, which existing heating methods do not adequately address.
Innovation Solution
The implementation of thermal annealing for flash memory cells using resistive heating generated by current flow in word lines, which induces high temperatures to repair damage and enhance charge storage characteristics, thereby improving endurance and erase speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional flash memory operations are performed without thermal annealing, then the device structure remains simple and operation is straightforward, but performance degradation occurs due to accumulated defects and trapped charges
Solution Approach 1:
The word lines serve dual functions: as control gates for memory cell selection during normal read/write operations and as resistive heating elements for thermal annealing. By applying current through the word lines, the patent achieves in-situ heating of the tunnel oxide without requiring separate heating circuitry, thus improving reliability while maintaining structural simplicity.
Solution Approach 2:
The flash memory device performs its own thermal annealing using its existing word line structures. The device utilizes its own operational components (word lines and control circuits) to generate the necessary heat for defect repair, eliminating the need for external or dedicated heating mechanisms and reducing overall device complexity.
2Reliability
If thermal annealing is applied to repair damage from program/erase cycling, then endurance is improved, but additional time is required for the annealing process
Solution Approach 1:
The patent implements thermal annealing periodically after a predetermined number of program/erase cycles rather than continuously. The control circuit monitors the cycle count and triggers annealing operations at intervals, balancing the need for defect repair with the constraint of operational time. This periodic approach maintains endurance improvements while minimizing time loss.
Solution Approach 2:
The thermal annealing process is merged with existing erase operations. The patent applies heating current through word lines during or after erase cycles, combining two functions (erasing and annealing) into a single operational sequence. This integration reduces the total time required compared to performing separate annealing steps.
3Temperature
If segmented word lines are used for thermal annealing, then heating efficiency and temperature control are improved, but device structure and wiring become more complex
Solution Approach 1:
The patent divides the word line structure into multiple segments (first and second word line segments) that can be independently controlled. This segmentation allows selective heating of specific memory regions and better temperature control during annealing operations. The segmented structure enables localized thermal management while maintaining compatibility with standard flash memory architectures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly enhances the endurance of flash memory devices to over 1 million cycles and improves erase speed by thermally assisting electron de-trapping and hole tunneling, breaking through the endurance bottleneck of traditional flash memory.
Implementation Method 1
heating circuitry disposed in proximity to the structures to heat the structures to a temperature that reverses the degradation. The word lines or the bit lines of the memory device are used as heating elements.
Data Source
Figure 1A~1C
Figure 2
Figure 3
AI summary
A memory includes an array of memory cells including rows and columns. The memory includes circuitry coupled to the word lines applying a first bias voltage to a first set of spaced-apart locations on a word line or word lines in the array, while applying a second bias voltage different than the first bias voltage, to a second set of spaced-apart locations on the word line or word lines, locations in the first set of spaced-apart locations being interleaved among locations in the second set of spaced-apart locations, whereby current flow is induced between locations in the first and second sets of locations that cause heating of the word line or word lines.