Electrostatic Discharge Protection Circuit Using Amorphous Silicon
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Solution Overview
Problem
Existing display devices face challenges in efficiently utilizing the amorphous silicon region, which is not fully leveraged due to the dominance of polycrystalline silicon regions, particularly in the context of electrostatic discharge protection circuits.
Innovation Solution
The implementation of an electrostatic discharge protection circuit within the amorphous silicon region, rather than the polycrystalline silicon region, allowing for selective crystallization and efficient use of amorphous silicon, along with the formation of transistors and a buffer layer, and the application of bias voltage to enhance transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the electrostatic discharge protection circuit is formed using polycrystalline silicon region, then the transistor performance and switching speed are improved, but the area utilization and productivity are reduced due to the large area required for polycrystalline silicon crystallization
Solution Approach 1:
The patent applies local quality by forming polycrystalline silicon only in specific regions where high-performance transistors are needed (such as switching elements and driving elements), while using amorphous silicon in other regions for electrostatic discharge protection circuits. This selective crystallization approach optimizes transistor performance where required while maximizing area utilization and productivity in other circuit regions.
2Reliability
If the entire amorphous silicon layer is crystallized into polycrystalline silicon, then the transistor performance is improved, but the manufacturing complexity and processing time are increased
Solution Approach 1:
The patent segments the amorphous silicon layer into multiple regions with different crystallization states: polycrystalline silicon regions for high-performance transistors and amorphous silicon regions for electrostatic discharge protection circuits. This segmentation allows different process treatments for different functional requirements, reducing overall manufacturing complexity and processing time while maintaining necessary performance levels.
3Productivity
If the electrostatic discharge protection circuit is formed in amorphous silicon region, then the area utilization and productivity are improved, but the transistor switching speed may be reduced
Solution Approach 1:
The patent applies local quality by assigning different material states to different functional regions: amorphous silicon for electrostatic discharge protection circuits where high switching speed is not critical, and polycrystalline silicon for switching elements and driving elements where high-speed operation is essential. This regional differentiation maximizes productivity while maintaining adequate performance for each circuit function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases productivity by reducing the area required for polycrystalline silicon, effectively utilizing the amorphous silicon region for electrostatic discharge protection while maintaining adequate performance, thus enhancing the overall efficiency and yield of display devices.
Implementation Method 1
crystallizing a partial region of the amorphous silicon layer into a polycrystalline silicon layer
Implementation Method 2
the amorphous silicon is irradiated with laser to thereby be crystallized into polycrystalline silicon
Data Source
AI summary
A method of manufacturing a display device including an electrostatic discharge protection circuit, the method including: forming an amorphous silicon layer on a substrate; crystallizing a partial region of the amorphous silicon layer into a polycrystalline silicon layer; and forming at least one transistor on the amorphous silicon layer that was not crystallized into the polycrystalline layer, wherein the electrostatic discharge protection circuit comprises the at least one transistor.