Metallic Etch Stop Layer for 3D Memory Fabrication
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Solution Overview
Problem
Current three-dimensional memory structures, such as vertical NAND strings, face challenges in efficiently forming monolithic memory arrays with reduced collateral etching and damage to dielectric liners during the fabrication process.
Innovation Solution
A method involving the formation of a dielectric liner on a semiconductor substrate, followed by a bottom conductive layer and a stack of alternating insulator and spacer material layers, where memory openings are created using an anisotropic etch process with the conductive layer as an etch stop, allowing for the formation of memory films and semiconductor channels within these openings, ensuring minimal collateral etching and damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used to form memory openings in three-dimensional memory structures, then memory openings can be formed, but collateral etching into the semiconductor substrate occurs causing damage to the dielectric liner
Solution Approach 1:
A bottom conductive layer is formed on the semiconductor substrate before forming the memory openings. This preliminary layer serves as an etch stop layer that prevents collateral etching into the substrate during subsequent etching processes, while still allowing memory openings to be formed through the alternating insulator and conductive layers above it.
Solution Approach 2:
The bottom conductive layer acts as an intermediary between the etching process and the semiconductor substrate. It provides a protective function by stopping the etch before it reaches the substrate, thereby protecting the dielectric liner from damage while still permitting the formation of memory openings.
2Object-affected harmful factors
If the bottom conductive layer is used as an etch stop layer, then collateral etching is reduced, but the etching process becomes more complex requiring selective etching through multiple layers
Solution Approach 1:
The etching process utilizes parameter changes by employing different etch selectivities for different material layers. The bottom conductive layer has distinct etching parameters compared to the alternating insulator and conductive layers, allowing selective removal of materials above the etch stop while preserving the substrate and dielectric liner below.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of monolithic three-dimensional NAND memory devices with reduced collateral etching into the semiconductor substrate and minimized damage to the dielectric liner, improving the integrity and efficiency of the memory structure formation.
Implementation Method 1
A memory opening extending through the stack is formed by an anisotropic etch process that employs the bottom conductive layer as an etch stop layer
Implementation Method 2
The memory opening is extended downward by etching through a first physically exposed portion of the bottom conductive layer and a first physically exposed portion of the dielectric liner
Data Source
AI summary
A dielectric liner, a bottom conductive layer, and a stack of alternating layers including insulator layers and spacer material layers are sequentially formed over a substrate. A memory opening extending through the stack can be formed by an anisotropic etch process that employs the bottom conductive layer as an etch stop layer. The memory opening is extended downward by etching through the bottom conductive layer and the dielectric liner, while minimizing an overetch into the substrate. A memory stack structure can be formed in the memory opening. Subsequently, a backside contact trench can be formed through the stack employing the bottom conductive layer as an etch stop layer. The spacer material layers can be removed to form backside recesses, which are filled with a conductive material to form electrically conductive layers. The remaining portion of the bottom conductive layer can be employed as a source select gate electrode.