Gate-All-Around Transistor Structure for Short-Channel Control
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Solution Overview
Problem
The reduction in transistor size in semiconductor devices leads to a short channel effect, which existing technologies like FinFETs and gate-all-around FETs struggle to mitigate effectively, resulting in performance and manufacturing yield issues.
Innovation Solution
A semiconductor device design featuring a channel with source and drain structures on opposing sides, a gate structure that surrounds the channel, and spacer layers to manage thickness uniformity and etching processes, enhancing hole mobility and manufacturing yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor size is reduced to increase device density, then productivity is improved, but short channel effect worsens causing performance degradation
Solution Approach 1:
The patent transitions from planar 2D channel structure to three-dimensional FinFET structure with vertical fins extending from the substrate. This dimensional change increases the effective channel area and device density while maintaining adequate gate control over the channel, thereby mitigating short channel effects that plague scaled planar transistors.
Solution Approach 2:
The gate structure completely surrounds the channel in a three-dimensional configuration, with the gate electrode wrapping around the fin structure on multiple sides. This nested arrangement provides enhanced gate control over the channel while maintaining compact device footprint, addressing both density and reliability requirements.
2Productivity
If transistor size is reduced, then device density increases, but manufacturing precision deteriorates due to process variability
Solution Approach 1:
The device structure is segmented into distinct functional layers including substrate, fin structures, gate electrode, gate insulator, and source/drain regions. Each layer can be independently optimized and controlled during manufacturing, improving process precision while enabling high device density through systematic layout.
Solution Approach 2:
The patent employs multiple material compositions with different etch selectivities (silicon nitride, silicon oxide, silicon germanium) to enable precise control of layer thicknesses and dimensions. By changing material parameters rather than simply scaling dimensions, manufacturing precision is maintained while achieving higher device density.
3Reliability
If gate structure completely surrounds channel to improve control, then reliability improves, but device complexity increases
Solution Approach 1:
The three-dimensional gate structure serves multiple functions simultaneously: it provides electrical control of the channel, acts as a structural framework defining the fin geometry, and enables capacitive coupling for device operation. This multi-functionality reduces the need for separate components, offsetting the increased structural complexity.
4Reliability
If source and drain layers are made thinner to reduce resistance, then electrical conductivity improves, but manufacturing precision worsens due to etching variability
Solution Approach 1:
Spacer layers of silicon nitride and silicon oxide are introduced as intermediary structures between the gate and source/drain regions. These spacers serve as etch masks and thickness reference layers, enabling precise control of source/drain layer dimensions while maintaining low resistance through optimized thickness and doping.
Solution Approach 2:
The source and drain structures employ composite material systems including silicon germanium alloys with varying germanium concentrations. This compositional variation enables tailored electrical properties and etch selectivity, allowing thin layers with low resistance while maintaining manufacturing precision through differential etching processes.
Data Source
AI summary
A semiconductor device includes a channel, a first source/drain structure on a first side surface of the channel, a second source/drain structure on a second side surface of the channel, a gate structure surrounding the channel, an inner spacer layer on a side surface of the gate structure, and an outer spacer layer on an outer surface of the inner spacer layer. The first source/drain structure includes a first source/drain layer on the channel and a second source/drain layer on the first source/drain layer, and on a plane of the semiconductor device that passes through the channel, at least one of a first boundary line of the first source/drain layer in contact with the second source/drain layer and a second boundary line of the first source/drain layer in contact with the channel may be convex, extending toward the channel.