Backside Gate Isolation Features for FinFET Gate Coupling
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Solution Overview
Problem
As semiconductor technology advances towards smaller nodes, parasitic capacitance between gate structures in multi-gate MOSFETs, such as FinFETs and MBC transistors, degrades device performance by increasing circuit speed and cross-talk coupling, despite the use of low-k dielectric materials and trimming gate electrodes, which challenges the formation of effective gate isolation features.
Innovation Solution
The method involves forming gate isolation features from the backside of the substrate, which are self-aligned and extend through the gate structure, allowing for increased distance between adjacent gate structures by trimming gate electrodes, thereby reducing parasitic capacitance, and using a seal layer to replace dielectric fins for improved isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate critical dimensions are reduced to increase device density, then production efficiency and cost are improved, but parasitic capacitance between gate structures increases and device performance degrades
Solution Approach 1:
The patent introduces dielectric fins extending vertically from the substrate between adjacent gate structures, adding a vertical isolation dimension. This three-dimensional isolation structure increases the separation distance between gates without reducing the horizontal chip area, thereby reducing parasitic capacitance while maintaining high device density.
Solution Approach 2:
The patent uses low-k dielectric material for the dielectric fins to act as an intermediary between adjacent gate structures. This intermediate dielectric layer reduces the electric field coupling between gates, effectively lowering parasitic capacitance and cross-talk while allowing gates to remain in close proximity for high density.
2Object-affected harmful factors
If dielectric fins made of low-k dielectric material are used to improve isolation between gate structures, then parasitic capacitance is reduced, but isolation effectiveness is insufficient at further reduced gate critical dimensions
Solution Approach 1:
The patent employs composite material structures including dielectric fins with low-k dielectric material, potentially combined with other dielectric layers or materials. This composite approach leverages the low-k property for capacitance reduction while additional materials provide structural support and enhanced isolation, achieving both low parasitic capacitance and high isolation effectiveness.
3Productivity
If gate structures are placed closer together to increase functional density, then chip area utilization is improved, but cross-talk coupling between gates increases
Solution Approach 1:
By introducing vertical dielectric fins, the patent creates additional isolation space in the vertical dimension. This allows horizontal gate spacing to be reduced for high functional density while the vertical fins prevent direct electric field coupling, thereby reducing cross-talk despite close gate placement.
Data Source
AI summary
Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary manufacturing method includes providing a workpiece that includes a substrate, first channel members and second channel members over the substrate, a first gate structure engaging the first channel members, a second gate structure engaging the second channel members, a dielectric fin disposed between the first and second gate structures, an isolation feature disposed under the dielectric fin. The method also includes forming a metal cap layer at the frontside of the workpiece and depositing a dielectric feature on the dielectric fin. The dielectric feature dividing the metal cap layer into a first segment and a second segment. The method also includes etching the isolation feature to form a trench at the backside of the substrate, depositing a spacer on sidewalls of the trench, etching the dielectric fin from the trench, and depositing a seal layer in the trench.