Common-Base Bipolar Transistor Row for Uniform Parasitic Resistance
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Solution Overview
Problem
In phase-change memory arrays, the parasitic resistance between bipolar transistors and their contacting regions is non-uniform and high, limiting the density of memory cells and requiring a tradeoff between identical parasitic resistance and reduced surface area, which affects the performance and efficiency of memory cell access.
Innovation Solution
The implementation of a row of bipolar transistors with a common base and insulating trenches, where conductive bars extend through the trenches and insulator walls, reducing parasitic resistance by forming a comb-like structure with main and auxiliary conductive bars made of metal, which are connected to the base and interconnection network, thereby ensuring consistent and reduced resistance across all transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a common base is used for all transistors in a word line, then the parasitic resistance should be identical across all transistors, but the surface area increases and density decreases
Solution Approach 1:
The base contact region is segmented into multiple contact points along the base, with conductive bars connecting these contacts to the interconnection network. This segmentation allows the base to serve multiple transistors while maintaining controlled resistance paths, resolving the contradiction between identical parasitic resistance and surface area by distributing the contact function across multiple points rather than requiring a large continuous contact region.
Solution Approach 2:
The conductive bars extend vertically through insulator walls and trenches, utilizing the vertical dimension to connect the base to the interconnection network. This dimensional transition allows compact routing of multiple conductive paths without increasing lateral surface area, enabling identical parasitic resistance across transistors while maintaining high density.
2Quantity of substance
If memory cell density is increased, then the transistor row length is reduced, but the parasitic resistance becomes non-uniform and increases
Solution Approach 1:
Heavily doped regions are created at specific locations where conductive bars contact the base, providing locally enhanced conductivity. This local quality modification ensures that despite the reduced row length and increased density, the parasitic resistance remains uniform across all transistors by compensating for variations in contact geometry and material properties at each local contact point.
3Reliability
If conductive bars are added to reduce parasitic resistance, then resistance is reduced, but device complexity increases
Solution Approach 1:
The conductive bars serve multiple functions: they provide electrical connection between the base and interconnection network, establish controlled resistance paths, and enable compact routing in the vertical dimension. This multi-functionality reduces the need for separate structures, thereby limiting the increase in device complexity while achieving reduced parasitic resistance.
Solution Approach 2:
The conductive bars act as intermediary elements between the base region and the interconnection network, providing a controlled resistance interface. These intermediaries simplify the overall structure by consolidating multiple connection functions into single elements, rather than requiring complex direct connections between numerous base contacts and interconnection lines.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in smaller, identical parasitic resistances across all transistors, increasing memory cell density and reducing the length of transistor rows by approximately 35%, while maintaining effective insulation and connectivity.
Implementation Method 1
A conductive layer is coupled to the base and the conductive layer extends through the insulator walls and at least partially into the insulating trench
Implementation Method 2
an insulating trench extends in a second direction and is in contact with each bipolar transistor of the row of bipolar transistors
Data Source
AI summary
The disclosure relates to integrated circuits including one or more rows of transistors and methods of forming rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a first semiconductor layer having a plurality of first conduction regions, a second semiconductor layer having a second conduction region, a common base between the first semiconductor layer and the second semiconductor layer, and a plurality of insulator walls extending in a first direction. The first conduction regions are separated from one another by the insulator walls. The integrated circuit further includes an insulating trench extending in a second direction and in contact with each of the bipolar transistors of the row of bipolar transistors. A conductive layer is coupled to the base, and the conductive layer extends through the insulator walls and extends at least partially into the insulating trench.