Vertical Gate Electrode Stack for Low-Resistance Nanostructure Channels
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Solution Overview
Problem
The semiconductor industry faces challenges in improving processing and manufacturing efficiency as the complexity of semiconductor integrated circuits (ICs) increases with scaling down, requiring innovative methods to enhance production efficiency and reduce costs while maintaining device performance.
Innovation Solution
The method involves forming a stack of semiconductor layers with alternating first and second layers of different etch selectivity and oxidation rates, using epitaxial growth processes, and employing advanced patterning and etching techniques to create nanostructure channels and gate electrode layers, including work function metal layers and conductive layers to reduce electrical resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then production efficiency is improved and costs are lowered, but processing complexity increases
Solution Approach 1:
The gate electrode layer is segmented into multiple conductive layers (first conductive layer, second conductive layer, third conductive layer) with different materials and properties. This segmentation allows each layer to be optimized for specific functions (work function adjustment, conductivity, stability) while collectively reducing overall electrical resistance, thereby improving production efficiency without excessive complexity increase
Solution Approach 2:
The gate electrode structure uses composite materials comprising multiple conductive layers with different compositions (e.g., tungsten, cobalt, copper, aluminum) and work function metal layers. This composite approach enables simultaneous optimization of electrical conductivity, work function, and thermal stability, addressing processing complexity while maintaining scaling benefits
2Quantity of substance
If functional density is increased by scaling down, then more interconnected devices fit per chip area, but manufacturing complexity increases
Solution Approach 1:
The gate electrode is divided into multiple conductive layers that can be deposited and patterned using standard semiconductor manufacturing processes. This segmentation allows incremental fabrication through sequential deposition steps, making high-density structures manufacturable with existing technology while achieving increased device density
Solution Approach 2:
The multi-layer gate electrode structure serves multiple functions simultaneously: providing electrical conductivity, adjusting work function for threshold voltage control, ensuring thermal stability, and enabling planarization. This multi-functionality allows a single structural solution to address multiple manufacturing requirements, simplifying the overall manufacturing process despite high device density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of efficient semiconductor device structures with reduced electrical resistance and improved manufacturing processes, enhancing production efficiency and device performance while maintaining cost-effectiveness.
Implementation Method 1
forming a stack of semiconductor layers with alternating first and second layers of different etch selectivity and oxidation rates, using epitaxial growth processes
Data Source
AI summary
A semiconductor device structure, along with methods of forming such, are described. The structure includes a first plurality of vertically aligned semiconductor layers disposed over a substrate and a first gate electrode layer surrounding each of the first plurality of vertically aligned semiconductor layers. The first gate electrode layer includes first one or more work function metal layers disposed between adjacent semiconductor layers of the first plurality of vertically aligned semiconductor layers and two first conductive layers disposed on opposite sides of the first one or more work function metal layers. The first conductive layers include a material different from the first one or more work function metal layers. The first gate electrode layer further includes a second conductive layer disposed on the first conductive layers, and the second conductive layer and the first conductive layers include a same material.