Split-Gate Flash Cell Layout With Spacer-Defined Floating Gate
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Solution Overview
Problem
Existing methods for forming split gate non-volatile memory cells lack effective control over the formation of various elements, such as floating gates and polysilicon gates, which affects the performance and efficiency of memory cell fabrication.
Innovation Solution
A method involving the deposition and selective removal of polysilicon layers, with the formation of insulation spacers and conductive spacers to define the dimensions and positions of the gates, allowing for independent optimization of each gate's height and alignment, and the creation of a sharp edge on the floating gate for enhanced erase performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication methods are used to form split gate memory cells, then the basic structure can be created, but the formation of various elements (floating gates, polysilicon gates) lacks effective control
Solution Approach 1:
The patent divides the gate formation process into separate stages: first forming the floating gate using a initial polysilicon deposition, then forming the word line gate and erase gate using subsequent polysilicon depositions. Each gate structure is defined by its own insulation spacer, allowing independent control of dimensions and positions for each gate element without affecting others.
Solution Approach 2:
The patent performs preliminary actions by forming insulation spacers before depositing each polysilicon layer. The first insulation spacer is formed to define the floating gate position, followed by formation of second and third insulation spacers to define word line and erase gate positions. This preliminary spacer formation enables precise control of gate dimensions before the actual gate materials are deposited.
2Manufacturing precision
If additional masking steps are added to improve control over gate formation, then manufacturing precision improves, but device complexity and fabrication time increase
Solution Approach 1:
The patent employs self-aligned fabrication where each gate structure automatically defines the position of its corresponding insulation spacer. The floating gate's side surfaces serve as the alignment reference for the first insulation spacer, the word line gate's side surfaces define the second insulation spacer position, and the erase gate's side surfaces define the third insulation spacer position. This self-service alignment eliminates the need for separate masking steps to define gate positions.
Solution Approach 2:
The patent merges the alignment function into the gate structures themselves. Instead of using separate masking layers to define gate positions, the gate structures (floating gate, word line gate, erase gate) directly serve as the alignment references for forming their respective insulation spacers and subsequent gate elements, combining multiple functions into unified structures.
3Reliability
If independent optimization of each gate's height is implemented, then memory cell performance improves, but fabrication process complexity increases
Solution Approach 1:
The patent segments the gate formation into three independent polysilicon deposition processes, each controlled by its own insulation spacer. The first polysilicon deposition forms the floating gate with height controlled by the first insulation spacer thickness. The second polysilicon deposition forms the word line gate with height controlled by the second insulation spacer thickness. The third polysilicon deposition forms the erase gate with height controlled by the third insulation spacer thickness. This segmentation allows independent optimization of each gate's height for specific performance requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables self-aligned floating gates with defined dimensions, independently optimized word line and erase gates, and improved erase efficiency, allowing for better control over memory cell performance without requiring additional masking steps.
Implementation Method 1
forming a first polysilicon layer using a first polysilicon deposition over and insulated from a semiconductor substrate; forming a second polysilicon layer using a second polysilicon deposition, different from the first polysilicon deposition, over the substrate; forming a third polysilicon layer using a third polysilicon deposition, different from the first and second polysilicon depositions, over the substrate
Data Source
Figure 1A~1B
Figure 1C
Figure 2A
AI summary
A method of forming a memory device that includes forming a first polysilicon layer using a first polysilicon deposition over a semiconductor substrate, forming an insulation spacer on the first polysilicon layer, and removing some of the first polysilicon layer to leave a first polysilicon block under the insulation spacer. A source region is formed in the substrate adjacent a first side surface of the first polysilicon block. A second polysilicon layer is formed using a second polysilicon deposition. The second polysilicon layer is partially removed to leave a second polysilicon block over the substrate and adjacent to a second side surface of the first polysilicon block. A third polysilicon layer is formed using a third polysilicon deposition. The third polysilicon layer is partially removed to leave a third polysilicon block over the source region. A drain region is formed in the substrate adjacent to the second polysilicon block.